HYB18L256160B Datasheet, PDF (14/58 Pages) Qimonda AG – DRAMs for Mobile Applications 256-Mbit Mobile-RAM

Data Sheet
2.4
Commands
HY[B/E]18L256160B[C/F]L-7.5
256-Mbit Mobile-RAM
TABLE 8
Command Overview
Command
CS RAS CAS WE DQM Address Note
NOP DESELECT
HX X X X
X
1)
NO OPERATION
LH H H X
X
1)
ACT ACTIVE (Select bank and row)
LL
H HX
Bank / Row ²⁾
RD READ (Select bank and column and start read burst)
LH
L
H L/H Bank / Col ³⁾
WR WRITE (Select bank and column and start write burst)
LH
L
L L/H Bank / Col ³⁾
BST BURST TERMINATE or
DEEP POWER DOWN
LH H L X
X
4)
PRE PRECHARGE (Deactivate row in bank or banks)
LL
H LX
Code
5)
ARF AUTO REFRESH or
SELF REFRESH (enter self refresh mode)
LL
L
HX
X
6)7)
MRS MODE REGISTER SET
LL
L
LX
Op-Code
8)
–
Data Write / Output Enable
–– – – L
–
9)
–
Write Mask / Output Disable (High-Z)
––
–
–H
–
9)
1) DESELECT and NOP are functionally interchangeable.
2) BA0, BA1 provide bank address, and A0 - A12 provide row address.
3) BA0, BA1 provide bank address, A0 - A8 provide column address; A10 HIGH enables the Auto Precharge feature (non persistent), A10
LOW disables the Auto Precharge feature.
4) This command is BURST TERMINATE if CKE is HIGH, DEEP POWER DOWN if CKE is LOW. The BURST TERMINATE command is
defined for READ or WRITE bursts with Auto Precharge disabled only.
5) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
6) This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8) BA0, BA1 select either the Mode Register (BA0 = 0, BA1 = 0) or the Extended Mode Register (BA0 = 0, BA1 = 1); other combinations of
BA0, BA1 are reserved; A0 - A12 provide the op-code to be written to the selected mode register.
9) DQM LOW: data present on DQs is written to memory during write cycles; DQ output buffers are enabled during read cycles; DQM HIGH:
data present on DQs are masked and thus not written to memory during write cycles;
DQ output buffers are placed in High-Z state (two clocks latency) during read cycles.
Address (A0 - A12, BA0, BA1), write data (DQ0 - DQ15) and command inputs (CKE, CS, RAS, CAS, WE, DQM) are all
registered on the positive edge of CLK. Figure 5 shows the basic timing parameters, which apply to all commands and
operations.
Rev. 1.73, 2006-09
14
01302004-CZ2R-J9SE