MT9M114_16 Datasheet, PDF (56/62 Pages) ON Semiconductor – High-Definition (HD) System-On- A-Chip (SOC) Digital Image Sensor

MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig-
ital Image Sensor
Table 23:
AC Electrical Characteristics
EXTCLK = 6–54 MHz; VDD = VDD_PHY = 1.8V; VDD_IO = VAA = VDD_PLL = 2.8V; TJ = 25°C unless otherwise stated
Symbol Parameter
Conditions
Min
Typ
Max
f_EXTCLK
D_EXTCLK
t_JITTER
t_PD
t_PFH
t_PLH
t_PFL
t_PLL
t_CP
External clock frequency
External input clock duty cycle
External input clock jitter
PIXCLK to data valid
PIXCLK to FV HIGH
PIXCLK to LV HIGH
PIXCLK to FV LOW
PIXCLK to LV LOW
EXTCLK TO PIXCLK propagation
delay
PIXCLK slew rate
Slew = 4
Output slew rate
Slew = 4
t_PIXCLK = PICXCLK period
6
54
40
50
60
–
500
–
–
2
5
–
2
5
–
2
5
–
2
5
–
2
5
0.1 x t_PIXCLK
VDD_IO = 2.8V, PLL bypass, 6 MHz
–
0.647
–
EXTCLK, CLOAD = 35 pF
VDD_IO = 1.8V, PLL bypass, 6 MHz
–
0.27
–
EXTCLK, CLOAD = 35 pF
VDD_IO = 2.8V, PLL bypass, 6 MHz
–
0.229
–
EXTCLK, CLOAD = 35 pF
VDD_IO = 1.8V, PLL bypass, 6 MHz
–
0.112
–
EXTCLK, CLOAD = 35 pF
Notes: 1. VIH/VIL restrictions apply.
2. Based on lab measurements. Could vary with noisier system-level electronics.
Unit
MHz
%
ps
ns
ns
ns
ns
ns
ns
Notes
1
2
V/ns
V/ns
V/ns
V/ns
Figure 36: Parallel Pixel Bus Timing Diagram
Notes:
1. FRAME_VALID leads LINE_VALID by 6 PIXCLKs.
2. FRAME_VALID trails LINE_VALID by 6 PIXCLKs.
3. Dout[7:0], FRAME_VALID, and LINE_VALID are shown with respect to the falling edge of PIXCLK.
This feature is programmable and Dout[7:0], FRAME_VALID, and LINE_VALID can be synchronized
to the rising edge of PIXCLK.
4. Propagation delay is measured from 50% of rising and falling edges.
MT9M114/D Rev. 11, 2/16 EN
56
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