MT9M114_16 Datasheet, PDF (49/62 Pages) ON Semiconductor – High-Definition (HD) System-On- A-Chip (SOC) Digital Image Sensor

MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig-
ital Image Sensor
Single Write to Random Location
This sequence (Figure 33) begins with the master generating a start condition. The slave
address/data direction byte signals a write and is followed by the high then low bytes of
the register address that is to be written. The master follows this with the byte of write
data. The write is terminated by the master generating a stop condition.
Figure 33: Single Write to Random Location
Previous Reg Address, N
Reg Address, M M+1
S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A
Write Data ^A P
A
Sequential Write, Start at Random Location
This sequence (Figure 34) starts in the same way as the single write to random location
(Figure 33). Instead of generating a no-acknowledge bit after the first byte of data has
been transferred, the master generates an acknowledge bit, and continues to perform
byte writes until L bytes have been written. The write is terminated by the master gener-
ating a stop condition.
Figure 34: Sequential Write, Start at Random Location
Previous Reg Address, N
Reg Address, M M+1
S Slave Address 0 A Reg Address[15:8] A Reg Address[7:0] A
Write Data A
M+1
M+2
M+3
Write Data A
Write Data A
M+L-2
Write Data A
M+L-1
M+L
Write Data
A
AS
Patch RAM
MT9M114 has Patch Ram, this allows for issues to be fixed without changing silicon
version and also allows for new features to be added to the silicon.
The patch would come in the format of Load and Apply sections, the user needs to
implement both sections. Below includes detail of what can be achieved when in
different host states.
STANDBY- LOAD PATCHES ONLY
STREAMING- LOAD AND APPLY PATCHES
SUSPEND-LOAD AND APPLY PATCHES
MT9M114/D Rev. 11, 2/16 EN
49
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