MT9M114_16 Datasheet, PDF (11/62 Pages) ON Semiconductor – High-Definition (HD) System-On- A-Chip (SOC) Digital Image Sensor

MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig-
ital Image Sensor
Hard Reset
The MT9M114 enters the reset state when the external RESET_BAR signal is asserted
LOW, as shown in Figure 5. All the output signals will be in High-Z state. When OE_BAR
is in HIGH state, the outputs pins will be High-Z during the internal boot time
Figure 5: Hard Reset Operation
t₁
t₄
t₂
t₃
EXTCLK
RESET_BAR
SDATA
All Outputs Data Active
Mode
Reset
Internal Boot Time
Data Active controlled
by OE_BAR
Enter streaming mode
OE_BAR
Table 6: Hard Reset
Symbol
t₁
t₂
t₃
t₄
Definition
RESET_BAR pulse width
Active EXTCLK required after RESET_BAR asserted
Active EXTCLK required before RESET_BAR de-asserted
Internal boot time^{1, 2}
Min Typ Max
Unit
50
–
10
–
–
– ^{EXTCLK cycles}
10
–
–
–
44.5
–
ms
Notes: 1. 1. Under the condition of EXTCLK=24MHz and default settings with CONFIG=1.
2. The host should poll the Command register to determine when the device is initialized.
MT9M114/D Rev. 11, 2/16 EN
11
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