MT9M114_16 Datasheet, PDF (46/62 Pages) ON Semiconductor – High-Definition (HD) System-On- A-Chip (SOC) Digital Image Sensor

MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig-
ital Image Sensor
Slave Address
Message Byte
Acknowledge Bit
No-Acknowledge Bit
Stop Condition
Bits [7:1] of this byte represent the device slave address and bit [0] indicates the data
transfer direction. A “0” in bit [0] indicates a WRITE, and a “1” indicates a READ. If the
SADDR signal is driven LOW, then addresses used by the MT9M114 are R0x090 (write
address) and R0x091 (read address). If the SADDR signal is driven HIGH, then addresses
used by the MT9M114 are R0x0BA (write address) and R0x0BB (read address).
Message bytes are used for sending register addresses and register write data to the slave
device and for retrieving register read data. The protocol used is outside the scope of the
two-wire serial interface specification.
Each 8-bit data transfer is followed by an acknowledge bit or a no-acknowledge bit in the
SCLK clock period following the data transfer. The transmitter (which is the master when
writing, or the slave when reading) releases SDATA. The receiver indicates an acknowl-
edge bit by driving SDATA LOW. As for data transfers, SDATA can change when SCLK is
LOW and must be stable while SCLK is HIGH.
The no-acknowledge bit is generated when the receiver does not drive SDATA low during
the SCLK clock period following a data transfer. A no-acknowledge bit is used to termi-
nate a read sequence.
A stop condition is defined as a LOW -to-HIGH transition on SDATA while SCLK is HIGH.
Typical Serial Transfer
A typical read or write sequence begins by the master generating a start condition on the
bus. After the start condition, the master sends the 8-bit slave address/data direction
byte. The last bit indicates whether the request is for a read or a write, where a “0” indi-
cates a write and a “1” indicates a read. If the address matches the address of the slave
device, the slave device acknowledges receipt of the address by generating an acknowl-
edge bit on the bus.
If the request was a write, the master then transfers the 16-bit register address to which a
write should take place. This transfer takes place as two 8-bit sequences and the slave
sends an acknowledge bit after each sequence to indicate that the byte has been
received. The master then transfers the data as an 8-bit sequence; the slave sends
acknowledge bit at the end of the sequence. After 8 bits have been transferred, the slave’s
internal register address is automatically incremented, so that the next 8 bits are written
to the next register address. The master stops writing by generating a (re)start or stop
condition.
If the request was a read, the master sends the 8-bit write slave address/data direction
byte and 16-bit register address, just as in the write request. The master then generates a
(re)start condition and the 8-bit read slave address/data direction byte, and clocks out
the register data, 8 bits at a time. The master generates an acknowledge bit after each 8-
bit transfer. The slave’s internal register address is automatically incremented after every
8 bits are transferred. The data transfer is stopped when the master sends a no-acknowl-
edge bit.
MT9M114/D Rev. 11, 2/16 EN
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