MT9M114_16 Datasheet, PDF (5/62 Pages) ON Semiconductor – High-Definition (HD) System-On- A-Chip (SOC) Digital Image Sensor

MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig-
ital Image Sensor
Sensor Core
The MT9M114 has a color image sensor with a Bayer color filter arrangement and a
1.2Mp active-pixel array with electronic rolling shutter (ERS). The sensor core readout is
10 bits and can be flipped and/or mirrored. The sensor core also supports separate
analog and digital gain for all four color channels (R, Gr, Gb, B).
Image Flow Processor (IFP)
The advanced IFP features and flexible programmability of the MT9M114 can enhance
and optimize the image sensor performance. Built-in optimization algorithms enable
the MT9M114 to operate with factory settings as a fully automatic and highly adaptable
system-on-a-chip (SOC) for most camera systems.
These algorithms include black level conditioning, shading correction, defect correc-
tion, color interpolation, edge detection, color correction, vertical perspective correc-
tion, aperture correction, and image formatting with cropping and scaling.
Microcontroller Unit (MCU)
The MCU communicates with all functional blocks by way of an internal ON Semicon-
ductor proprietary bus interface. The MCU firmware configures all the registers in the
sensor core and IFP.
System Control
The MT9M114 has a phase-locked loop (PLL) oscillator that can generate the internal
sensor clock from a common wireless system clock. The PLL adjusts the incoming clock
frequency up, allowing the MT9M114 to run at almost any desired resolution and frame
rate within the sensor’s capabilities. Low-power consumption is a very important
requirement.
The MT9M114 provides power-conserving features including a soft standby mode. A
two-wire serial interface bus enables read and write access to the MT9M114’s internal
registers and variables. The internal registers control the sensor core, the color pipeline
flow, and the output interface. Variables are located in the microcontroller's RAM
memory and are used to configure and control the auto-algorithms and camera control
functions.
Output Interface
The output interface block can select either raw data or processed data. Image data is
provided to the host system either by an 8-bit parallel port or by a serial MIPI port. The
parallel output port provides 8-bit RGB data or extended 10-bit Bayer data.
The MT9M114 also includes programmable I/O slew rate to minimize EMI.
System Interfaces
Figure 2 on page 6 shows typical MT9M114 device connections. For low-noise operation,
the MT9M114 requires separate power supplies for analog and digital sections of the die.
Both power supply rails must be decoupled from ground using capacitors as close as
possible to the die. The use of inductance filters is not recommended on the power
supplies or output signals.
The MT9M114 provides dedicated signals for digital core, PHY, and I/O power domains
that can be at different voltages. The PLL and analog circuitry require clean power
sources. Table 3 on page 7 provides the signal descriptions for the MT9M114.
MT9M114/D Rev. 11, 2/16 EN
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