MT9M114_16 Datasheet, PDF (12/62 Pages) ON Semiconductor – High-Definition (HD) System-On- A-Chip (SOC) Digital Image Sensor

MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig-
ital Image Sensor
Soft Reset
The host processor can reset the MT9M114 using the two-wire serial interface by writing
to SYSCTL 0x001A. SYSCTL 0x001A[0] is used to reset the MT9M114 which is similar to
external RESET_BAR signal.
1. Set SYSCTL 0x001A[0] to 0x1 to initiate internal reset cycle.
2. Reset SYSCTL 0x001A[0] to 0x0 for normal operation.
3. Delay of 44.5 ms.
Figure 6: Soft Reset Operation
t1
EXTCLK
SCLK
SDATA
Mode
Write Soft
Reset Command
Resetting Registers
Enter Streaming Mode
Table 7: Soft Reset Signal Timing
Symbol
t₁
Parameter
Soft reset time^{1, 2}
Min Typ Max
Unit
–
44.5
–
ms
Notes: 1. Under the condition of EXTCLK=24MHz and default settings with CONFIG=1.
2. The host should poll the Command register to determine when the device is initialized.
Soft Standby Mode
The MT9M114 can enter soft standby mode by receiving a host command through the
two-wire serial interface. EXTCLK can be stopped to reduce the power consumption
during soft standby mode. However, since two-wire serial interface requires EXTCLK to
operate, ON Semiconductor recommends that EXTCLK run continuously.
Entering Standby Mode
1. Send the sequence [Enter Standby] to put the MT9M114 into standby.
[Enter Standby]
FIELD_WR= SYSMGR_NEXT_STATE, 0x50
// (Optional) First check that the FW is ready to accept a new command
ERROR_IF= COMMAND_REGISTER, HOST_COMMAND_1, !=0, "Set State cmd bit
is already set"
// (Mandatory) Issue the Set State command
// We set the 'OK' bit so we can detect if the command fails
// Note 0x8002 is equivalent to (HOST_COMMAND_OK | HOST_COMMAND_1)
FIELD_WR= COMMAND_REGISTER, 0x8002
MT9M114/D Rev. 11, 2/16 EN
12
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