MT9M114_16 Datasheet, PDF (45/62 Pages) ON Semiconductor – High-Definition (HD) System-On- A-Chip (SOC) Digital Image Sensor

MT9M114: 1/6-Inch 720p High-Definition (HD) System-On-A-Chip (SOC) Dig-
ital Image Sensor
Once this constraint has been met, the MT9M114 devices are required to operate in
exact synchronisation (such that a PIXCLK, FRAME_VALID and LINE_VALID out of one
MT9M114 is valid for all MT9M114 in the daisy-chain). In this case, the MT9M114
internal PLL must be bypassed (and the MT9M114 must be using parallel output data).
This feature can be used with the MIPI interface and PLL enabled, in that case the
signals will be synchronized up to an accuracy of 2 PIXCLK cycles.
Hardware Functions
Two-Wire Serial Interface
The two-wire serial interface bus enables read and write access to control and status
registers and variables within the MT9M114.
The interface protocol uses a master/slave model in which a master controls one or
more slave devices. The MT9M114 always operates in slave mode. The host (master)
generates a clock (SCLK) that is an input to the MT9M114 and is used to synchronize
transfers. Data is transferred between the master and the slave on a bidirectional signal
(SDATA).
The host should always ensure that the following relationship is adhered to.
SCLK (PIXEL CLOCK/22)
Protocol
Data transfers on the two-wire serial interface bus are performed by a sequence of low-
level protocol elements, as follows:
1. a (repeated) start condition
2. a slave address/data direction byte
3. a 16-bit register address (8-bit addresses are not supported)
4. an (a no) acknowledge bit
5. a 16-bit data transfer (8-bit data transfers are not supported)
6. a stop condition
The bus is idle when both SCLK and SDATA are HIGH. Control of the bus is initiated with
a start condition, and the bus is released with a stop condition. Only the master can
generate the start and stop conditions.
A start condition is defined as a HIGH-to-LOW transition on SDATA while SCLK is HIGH.
At the end of a transfer, the master can generate a start condition without previously
generating a stop condition; this is known as a repeated start or restart condition.
A stop condition is defined as a LOW-to-HIGH transition on SDATA while SCLK is HIGH.
Data is transferred serially, 8 bits at a time, with the most significant bit (MSB) trans-
mitted first. Each byte of data is followed by an acknowledge bit or a no-acknowledge bit.
This data transfer mechanism is used for the slave address/data direction byte and for
message bytes. One data bit is transferred during each SCLK clock period. SDATA can
change when SCLK is LOW and must be stable while SCLK is HIGH.
MT9M114/D Rev. 11, 2/16 EN
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