MC68HC05C8A Datasheet, PDF (94/158 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA = 1, the SS pin may
be thought of as a simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Select Bits
These two bits select one of four baud rates to be used as SCK if the
device is a master; however, they have no effect in the slave mode.
See Table 10-1.
Table 10-1. Serial Peripheral Rate Selection
SPR1
0
0
1
1
SPR0
0
1
0
1
Bus Clock Divided By
2
4
16
32
10.6.2 Serial Peripheral Status Register
Address: $000B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
0
0
0
0
SPIF WCOL
MODF
Write:
Reset 0
0
0
0
0
0
U
U
= Unimplemented
U = Unaffected
Figure 10-5. SPI Status Register (SPSR)
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Unless SPSR is read
(with SPIF set) first, attempts to write to SPDR are inhibited.
Technical Data
94
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A — Rev. 5.0
Serial Peripheral Interface (SPI)
MOTOROLA