MC68HC05C8A Datasheet, PDF (92/158 Pages) Motorola, Inc – Microcontrollers

Serial Peripheral Interface (SPI)
In a slave mode, the slave select start logic receives a logic low at the
SS pin and a clock at the SCK pin. Thus, the slave is synchronized with
the master. Data from the master is received serially at the MOSI line
and loads the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from
the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave
interconnections.
SPI SHIFT REGISTER
PD3/MOSI
PD2/MISO
PD5
I/O PORT
SS
SPDR ($000C)
PD4/SCK
SPI SHIFT REGISTER
SPDR ($000C)
MASTER MCU
SLAVE MCU
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
10.6 SPI Registers
This subsection describes the three registers in the SPI which provide
control, status, and data storage functions. These registers are:
• Serial peripheral control register (SPCR)
• Serial peripheral status register (SPSR)
• Serial peripheral data I/O register (SPDR)
Technical Data
92
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A — Rev. 5.0
Serial Peripheral Interface (SPI)
MOTOROLA