MC68HC05C8A Datasheet, PDF (48/158 Pages) Motorola, Inc – Microcontrollers

Resets
5.3 Power-On Reset (POR)
An internal reset is generated on power-up to allow the internal clock
generator to stabilize. The power-on reset is strictly for power turn-on
conditions and should not be used to detect a drop in the power supply
voltage. There is a 4064 internal processor clock cycle (t_CYC) oscillator
stabilization delay after the oscillator becomes active. If the RESET pin
is low after the end of this 4064-cycle delay, the MCU will remain in the
reset condition until RESET goes high.
For additional information, refer to Figure 13-8. Power-On Reset
Timing Diagram.
5.4 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a
period of one and one-half machine cycles (t_RL).
5.5 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature as a mask option. The
COP is implemented with an 18-bit ripple counter. This provides a
timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP
should time out, a system reset will occur and the device will be
re-initialized in the same fashion as a power-on reset (POR) or external
reset.
5.5.1 Resetting the COP
Preventing a COP reset is done by writing a logic 0 to the COPC bit. This
action will reset the counter and begin the timeout period again. The
COPC bit is bit 0 of address $1FF0. A read of address $1FF0 will result
in the user defined ROM data at that location.
Technical Data
48
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A — Rev. 5.0
Resets
MOTOROLA