MC68HC05C8A Datasheet, PDF (77/158 Pages) Motorola, Inc – Microcontrollers

Serial Communications Interface (SCI)
SCI Operation
9.5.2.4 Receiver Noise Immunity
The data recovery logic samples each bit 16 times to identify and verify
the start bit and to detect noise. Any conflict between noise-detection
samples sets the noise flag (NF) in the SCSR. The NF bit is set at the
same time that the RDRF bit is set.
9.5.2.5 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error (FE) bit in
the SCSR. The FE bit is set at the same time that the RDRF bit is set.
9.5.2.6 Receiver Interrupts
Three sources can generate SCI receiver interrupt requests:
1. Receive data register full (RDRF) — The RDRF bit in the SCSR
indicates that the receive shift register has transferred a character
to the SCDR.
2. Receiver overrun (OR) — The OR bit in the SCSR indicates that
the receive shift register shifted in a new character before the
previous character was read from the SCDR.
3. Idle input (IDLE) — The IDLE bit in the SCSR indicates that 10 or
11 consecutive logic 1s shifted in from the PD0/RDI pin.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A — Rev. 5.0
MOTOROLA
Serial Communications Interface (SCI)
Technical Data
77