MC68HC05C8A Datasheet, PDF (82/158 Pages) Motorola, Inc – Microcontrollers

Serial Communications Interface (SCI)
9.6.4 SCI Status Register
The SCI status register contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
Read: TDRE
TC
RDRF IDLE
OR
NF
FE
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-7. SCI Status Register (SCSR)
TDRE — Transmit Data Register Empty Bit
This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set, and then writing to the SCDR.
Reset sets the TDRE bit. Software must initialize the TDRE bit to logic
0 to avoid an instant interrupt request when turning on the transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Bit
This clearable, read-only bit is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TC generates
an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC
bit by reading the SCSR with TC set, and then writing to the SCDR.
Technical Data
82
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A — Rev. 5.0
Serial Communications Interface (SCI)
MOTOROLA