MC68HC05C8A Datasheet, PDF (63/158 Pages) Motorola, Inc – Microcontrollers

15
COUNTER HIGH BYTE
0
COUNTER LOW BYTE
16-BIT COMPARATOR
15
87
0
OUTPUT COMPARE REGISTER HIGH OUTPUT COMPARE REGISTER LOW
Timer
Input Capture Register
PIN
CONTROL
LOGIC
TCMP
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
$0012
TIMER STATUS REGISTER
$0013
Figure 8-2. Output Compare Operation
8.5 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are
read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition. The level transition which triggers the counter transfer is
defined by the corresponding input edge bit (IEDG). Reset does not
affect the contents of the input capture register except when exiting stop
mode.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (ICF) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A — Rev. 5.0
MOTOROLA
Timer
Technical Data
63