MC68HC05C8A Datasheet, PDF (93/158 Pages) Motorola, Inc – Microcontrollers

10.6.1 Serial Peripheral Control Register
Serial Peripheral Interface (SPI)
SPI Registers
Address: $000A
Bit 7
6
5
4
3
2
1
Read:
SPIE
SPE
Write:
MSTR CPOL CPHA SPR1
Reset 0
0
0
0
0
0
U
= Unimplemented
U = Unaffected
Figure 10-4. SPI Control Register (SPCR)
Bit 0
SPR0
U
SPIE — Serial Peripheral Interrupt Enable Bit
0 = SPIF interrupts disabled
1 = SPI interrupt is enabled
SPE — Serial Peripheral System Enable Bit
0 = SPI system off
1 = SPI system on
MSTR — Master Mode Select Bit
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit also is used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See Figure 10-1.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A — Rev. 5.0
MOTOROLA
Serial Peripheral Interface (SPI)
Technical Data
93