MC68HC05C8A Datasheet, PDF (66/158 Pages) Motorola, Inc – Microcontrollers

Timer
Bits 2, 3, and 4 — Not used
Always read 0
8.7 Timer Status Register
The timer status register (TSR) is a read-only register containing three
status flag bits.
Technical Data
66
Address: $0013
Bit 7
6
5
4
3
2
1
Bit 0
Read: ICF
OCF
TOF
0
0
0
0
0
Write:
Reset: U
U
U
0
0
0
0
0
= Unimplemented U = Unaffected
Figure 8-5. Timer Status Register (TSR)
ICF — Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture
edge detector
0 = Flag cleared when TSR and input capture low register ($15) are
accessed
OCF — Output Compare Flag
1 = Flag set when output compare register contents match the free-
running counter contents
0 = Flag cleared when TSR and output compare low register ($17)
are accessed
TOF — Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to
$0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are
accessed
Bits 0–4 — Not used
Always read 0
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A — Rev. 5.0
Timer
MOTOROLA