MC68HC05C8A Datasheet, PDF (84/158 Pages) Motorola, Inc – Microcontrollers

Serial Communications Interface (SCI)
FE — Receiver Framing Error Flag
This clearable, read-only flag is set when there is a logic 0 where a
stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR bit is set and the FE bit is not set. Clear the FE
bit by reading the SCSR, and then reading the SCDR. Reset clears
the FE bit.
1 = Framing error
0 = No framing error
9.6.5 Baud Rate Register
The baud rate register (BAUD) selects the baud rate for both the receiver
and the transmitter.
Address: $000D
Bit 7
6
5
4
3
2
1
Read:
0
Write:
0
SCP1 SCP0
0
SCR2 SCR2
Reset: 0
0
0
0
0
U
U
U = Unaffected
Figure 9-8. Baud Rate Register (BAUD)
Bit 0
SCR0
U
SCP1 and SCP0 — SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 9-1. Resets clear both SCP1 and SCP0.
Table 9-1. Baud Rate Generator Clock Prescaling
SCP0–SCP1
00
01
10
11
Baud Rate Generator Clock
Internal clock divided by 1
Internal clock divided by 3
Internal clock divided by 4
Internal clock divided by 13
Technical Data
84
MC68HC05C8A • MC68HCL05C8A • MC68HSC05C8A — Rev. 5.0
Serial Communications Interface (SCI)
MOTOROLA