M37280MF Datasheet, PDF (76/178 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
The vertical position for each block can be set in 1024 steps (where
each step is 1TH (TH: HSYNC cycle)) as values “0016” to “FF16” in
vertical position register 1i (i = 1 to 16) (addresses 022016 to 022F16)
and values “0016” to “0316” in vertical position register 2i (i = 1 to 16)
(addresses 023016 to 023F16). The vertical position registers are
shown in Figures 12.11.10 and 12.11.11.
Vertical Position Register 1i
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register 1i (VP1i) (i = 1 to 16) [Addresses 022016 to 022F16]
B
Name
Functions
After reset R W
0 Control bits of vertical Vertical display start positions
Indeterminate R W
to ^{display start positions (low-order 8 bits)}
7 ^{(VP1i0 to VP1i7)}
(See note 1)
TH !
(setting value of low-order 2 bits of VP2i ! 16²
+ setting value of low-order 4 bits of VP1i ! 16¹
+ setting value of low-order 4 bits of VP1i ! 16⁰)
Notes 1: Do not “0016” and “0116” to VP1i at VP2i = “0016.”
2: TH is cycle of HSYNC.
3: VP2i is vertical position register 2i.
Fig. 12.11.10 Vertical Position Register 1i (i = 1 to 16)
Vertical Position Register 2i
b7 b6 b5 b4 b3 b2 b1 b0
Vertical position register 2i (VP2i) (i = 1 to 16) [Addresses 023016 to 023F16]
B
Name
0, 1 _{Control bits of vertical}
display start positions
(VP2i0, VP2i1)
(See note 1)
Functions
Vertical display start positions
(high-order 2 bits)
TH !
(setting value of low-order 2 bits of VP2i ! 16²
+ setting value of low-order 4 bits of VP1i ! 16¹
+ setting value of low-order 4 bits of VP1i ! 16⁰)
After reset
Indeterminate
RW
RW
2 _{Nothing is assigned. These bits are write disable bits.}
Indeterminate R —
to _{When these bits are read out, the values are indeterminate.}
7
Notes 1: Do not set “0016” and “0116” to VP1i at VP2i = “0016.”
2: TH is cycle of HSYNC.
3: VP1i is vertical position register 1i.
Fig. 12.11.11 Vertical Position Register 2i (i = 1 to 16)
Rev. 1.0
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