M37280MF Datasheet, PDF (64/178 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.10.11 16-bit Shift Register
The caption data converted into a digital value by the comparator is
stored into the 16-bit shift register in synchronization with the data
clock. The contents of the high-order 8 bits of the stored caption data
can be obtained by reading out data register 2 (address 00E316) and
data register 4 (address 00E516). The contents of the low-order 8
bits can be obtained by reading out data register 1 (address 00E216)
and data register 3 (address 00E416), respectively. These registers
are reset to “0” at a falling of Vsep. Read out data registers 1 and 2
after the occurrence of a data slicer interrupt (refer to “12.10.12 In-
terrupt Request Generating Circuit”).
12.10.12 Interrupt Request Generating Circuit
The interrupt requests as shown in Table 12.10.3 are generated by
combination of the following bits; bits 6 and 7 of the caption position
register (address 00E616). Read out the contents of data registers 1
to 4 and the contents of bits 3 to 7 of the clock run-in detect register
after the occurrence of a data slicer interrupt request.
Table 12.10.2 Contents of Caption Data Latch Completion Flag and 16-bit Shift Register
Slice Line Specification Mode
CPS
bit 7
bit 6
0
0
0
1
Contents of Caption Data Latch Completion Flag
Completion Flag 1
(bit 0 of DSC2)
Completion Flag 2
(bit 5 of CPS)
Line 21
A line specified by
bits 4 to 0 of CPS
A line specified by
bits 4 to 0 of CPS
Invalid
Contents of 16-bit Shift Register
Caption Data
Registers 1, 2
Caption Data
Registers 3, 4
16-bit data of line 21
16-bit data of a line specified
by bits 4 to 0 of CPS
16-bit data of a line specified by
bits 4 to 0 of CPS
Invalid
1
0
Line 21
Invalid
16-bit data of line 21
Invalid
1
1
CPS: Caption position register
DSC2: Data slicer control register 2
Line 21
A line specified by
bits 4 to 0 of CPS
16-bit data of line 21
16-bit data of a line specified by
bits 4 to 0 of CPS
Table 12.10.3 Occurence Sources of Interrupt Request
Caption position register
b7
b6
0
0
1
0
1
1
Occurence Souces of Interrupt Request at End of Data Slice Line
After slicing line 21
After a line specified by bits 4 to 0 of CPS
After slicing line 21
After slicing line 21
Rev. 1.0
64