M37280MF Datasheet, PDF (62/178 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.10.7 Reference Voltage Generating Circuit
and Comparator
The composite video signal clamped by the clamping circuit is input
to the reference voltage generating circuit and the comparator.
(1) Reference Voltage Generating Circuit
This circuit generates a reference voltage (slice voltage) by using
the amplitude of the clock run-in pulse in line specified by the
data slice line specification circuit. Connect a capacitor between
the VHOLD pin and the VSS pin, and make the length of wiring as
short as possible so that a leakage current may not be gener-
ated.
(2) Comparator
The comparator compares the voltage of the composite video
signal with the voltage (reference voltage) generated in the refer-
ence voltage generating circuit, and converts the composite video
signal into a digital value.
12.10.8 Start Bit Detecting Circuit
This circuit detects a start bit at line decided in the data slice line
specification circuit.
The detection of a start bit is described below.
ΠA sampling clock is generated by dividing the reference clock out-
put by the timing signal.
 A clock run-in pulse is detected by the sampling clock.
Ž After detection of the pulse, a start bit pattern is detected from the
comparator output.
12.10.9 Clock Run-in Determination Circuit
This circuit determinates clock run-in by counting the number of pulses
in a window of the composite video signal.
The reference clock count value in one pulse cycle is stored in bits 3
to 7 of the clock run-in detect register (address 00EA16). Read out
these bits after the occurrence of a data slicer interrupt (refer to
“12.10.12 Interrupt Request Generating Circuit”).
Figure 12.10.10 shows the structure of clock run-in detect register.
Clock Run-in Detect Register
b7 b6 b5 b4 b3 b2 b1 b0
Clock run-in detect register (CRD) [Address 00EA16]
B
Name
0 Test bits
to
2
3 Clock run-in detection
to bit(CRD3 to CRD7)
7
Functions
Read-only
After reset R W
0 R—
Number of reference clocks to
be counted in one clock run-in
pulse period.
0 R—
Fig. 12.10.10 Clock Run-in Detect Register
Rev. 1.0
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