M37280MF Datasheet, PDF (17/178 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

PRELIMINARY _{NSootimcee: pTahriasmisennotitcalimfinitasl} ^{asrpeecsiufibcjaetciot nto. change.}
MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
s SFR2 area (addresses 20016 to 21F16)
Bit allocation
:
: ^Name
Function bit
State immediately after reset
0 ^{: “0” immediately after reset}
1 : “1” immediately after reset
: No function bit
0 ^{: Fix to this bit to “0”}
(do not write to “1”)
1 : Fix to this bit to “1”
(do not write to “0”)
? : Indeterminate immediately
after reset
Address Register
20016 PWM0 register (PWM0)
20116
20216
20316
20416
20516
20616
PWM1 register (PWM1)
PWM2 register (PWM2)
PWM3 register (PWM3)
PWM4 register (PWM4)
PWM5 register (PWM5)
PWM6 register (PWM6)
20716 PWM7 register (PWM7)
20816
20916
20A16 _{PWM mode register 1 (PN)}
20B16 _{PWM mode register 2 (PW)}
20C16 ROM correction address 1 (high-order)
20D16 ROM correction address 1 (low-order)
20E16 ROM correction address 2 (high-order)
20F16 ROM correction address 2 (low-order)
21016 ROM correction enable register (RCR)
21116 ^{Test register}
21216 Interrupt input polarity register (IP)
21316 Serial I/O mode register (SM)
21416 Serial I/O register (SIO)
21516 OSD control register 2(OC2)
21616 Clock control register (CS)
21716 _{I/O polarity control register (PC)}
21816 Raster color register (RC)
21916 OSD control register 3(OC3)
21A16 Timer 5 (TM5)
21B16 Timer 6 (TM6)
21C16 Top border control register 1 (TB1)
21D16 _{Bottom border control register 1 (BB1)}
21E16 Top border control register 1 (TB2)
21F16 Bottom border control register 1 (BB2)
Bit allocation
b7
b0
PN4 PN3
PN0
PW7 PW6 PW5 PW4 PW3 PW2 PW1 PW0
AD/INT3 INT3
SEL POL
RE5
R0E3 R0E2 ^RR^CE^R1^{1 RCR0}
0016
AADD//IINNTT33
SSEELL
P^IPNO_OTL_L33
RE5
POL2 P_RO_EL₃1
RE2
RE1
AD/INT3
SEL
S^IPNOM^TL36
RSME55 SM4
RSME33
RSME22
RSME11
SM0
OC27 OC26 OC25 OC24 OC23 OC12 OC21 OC20
0 0 ^{AD/INT3 INT3}
SEL POL
0 0 RCES2 RCES1 CS0
AS_PDEL/_CINT₇3 _PIPNO_CTL3_{6 RPCE5 PC4 RE3 RPCE2 RPCE1 PC0}
AD/INT3 INT3
SEL POL
RE5 RC4 RCE3 REC2 REC1 RC0
OC37 OC36 OC35 OC34 ORCE333 ROCE322 ROCE311 OC30
TB17 TB16 TB15 TB14 TB13 TB12 TB11 TB10
BB17 BB16 BB15 BB14 BB13 BB12 BB11 BB10
TB21 TB20
BB21 BB20
State immediately after reset
b7
b0
?
?
?
?
?
?
?
?
?
?
0016
0016
0016
0016
0016
0016
0016
0016
0016
0016
?
0016
0016
8016
0016
0016
0716
FF16
?
?
?
?
Fig. 12.2.5 Memory Map of Special Function Register 2 (SFR2) (1)
Rev. 1.0
17