M37280MF Datasheet, PDF (60/178 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.10.6 Data Slice Line Specification Circuit
(1) Specification of Data Slice Line
This circuit decides a line on which caption data is superimposed.
The line 21 (fixed), 1 appropriate line for a period of 1 field (total 2
line for a period of 1 field), and both fields (F1 and F2) are sliced
their data. The caption position register (address 00E616) is used
for each setting (refer to Table 12.10.1).
The counter is reset at the falling edge of Vsep and is incremented
by 1 every Hsep pulse. When the counter value matched the value
specified by bits 4 to 0 of the caption position register, this Hsep is
sliced.
The values of “0016” to “1F16” can be set in the caption position
register (at setting only 1 appropriate line). Figure 12.10.8 shows
the signals in the vertical blanking interval. Figure 12.10.9 shows
the structure of the caption position register.
(2) Specification of Line to Set Slice Voltage
The reference voltage for slicing (slice voltage) is generated for
the clock run-in pulse in the particular line (refer to Table 7). The
field to generate slice voltage is specified by bit 1 of data slicer
control register 1. The line to generate slice voltage 1 field is speci-
fied by bits 6, 7 of the caption position register (refer to
Table 12.10.1).
(3) Field Determination
The field determination flag can be read out by bit 3 of data slicer
control register 2. This flag charge at the falling edge of Vsep.
Video signal
Composite
video signal
Vsep
Hsep
Vertical blanking interval
1 appropriate line is set by
the caption position register
(when setting line 19)
Line 21
Count value to be set in the caption position register (“0F16” in this case)
Magnified drawing
Hsep
Composite video
signal
Window for
deteminating
clock-run-in
Clock run-in
Start bit + 16-bit data
Start bit
Fig. 12.10.8 Signals in Vertical Blanking Interval
60
Rev. 1.0