M37280MF Datasheet, PDF (50/178 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
12.8 A-D CONVERTER
12.8.1 A-D Conversion Register (AD)
A-D conversion reigister is a read-only register that stores the result
of an A-D conversion. This register should not be read during A-D
conversion.
12.8.2 A-D Control Register (ADCON)
The A-D control register controls A-D conversion. Bits 2 to 0 of this
register select analog input pins. When these pins are not used as
anlog input pins, they are used as ordinary I/O pins. Bit 3 is the A-D
conversion completion bit, A-D conversion is started by writing “0” to
this bit. The value of this bit remains at “0” during an A-D conversion,
then changes to “1” when the A-D conversion is completed.
Bit 4 controls connection between the resistor ladder and VCC. When
not using the A-D converter, the resistor ladder can be cut off from
the internal VCC by setting this bit to “0,” accordingly providing low-
power dissipation.
12.8.3 Comparison Voltage Generator (Resis-
tor Ladder)
The voltage generator divides the voltage between VSS and VCC by
256, and outputs the divided voltages to the comparator as the refer-
ence voltage Vref.
12.8.4 Channel Selector
The channel selector connects an analog input pin, selected by bits
2 to 0 of the A-D control register, to the comparator.
12.8.5 Comparator and Control Circuit
The conversion result of the analog input voltage and the reference
voltage “Vref” is stored in the A-D conversion register. The A-D con-
version completion bit and A-D conversion interrupt request bit are
set to “1” at the completion of A-D conversion.
Data bus
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
b7
b0
A-D control register
(address 00EF16)
3
A-D control circuit
Compa-
rator
A-D conversion register
8 (address 00EE16)
Switch tree
Resistor ladder
VSS VCC
A-D conversion
interrupt request
Fig. 12.8.1 A-D Comparator Block Diagram
Rev. 1.0
50