M37280MF Datasheet, PDF (24/178 Pages) Mitsubishi Electric Semiconductor – SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER and ON-SCREEN DISPLAY CONTROLLER

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MITSUBISHI MICROCOMPUTERS
M37280MF–XXXSP, M37280MK–XXXSP
M37280EKSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
Interrupt Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 1 (ICON1) [Address 00FE16]
B
Name
0 Timer 1 interrupt
enable bit (TM1E)
Functions
0 : Interrupt disabled
1 : Interrupt enabled
After reset R W
0 RW
1 Timer 2 interrupt
enable bit (TM2E)
0 : Interrupt disabled
1 : Interrupt enabled
0 RW
2 Timer 3 interrupt
enable bit (TM3E)
0 : Interrupt disabled
1 : Interrupt enabled
0 RW
3 Timer 4 interrupt
enable bit (TM4E)
0 : Interrupt disabled
1 : Interrupt enabled
4 OSD interrupt enable bit 0 : Interrupt disabled
(OSDE)
1 : Interrupt enabled
0 RW
0 RW
5 VSYNC interrupt enable 0 : Interrupt disabled
bit (VSCE)
1 : Interrupt enabled
0 RW
6 A-D conversion • INT3
interrupt enable bit (ADE)
0 : Interrupt disabled
1 : Interrupt enabled
0 RW
7 Nothing is assigned. This bit is a write disable
bit. When this bit is read out, the value is “0.”
0 R—
Fig. 12.3.4 Interrupt Control Register 1
Interrupt Control Register 2
b7 b6 b5 b4 b3 b2 b1 b0
Interrupt control register 2 (ICON2) [Address 00FF16]
B
Name
Functions
0 INT1 interrupt
enable bit (IN1E)
0 : Interrupt disabled
1 : Interrupt enabled
1 Data slicer interrupt
enable bit (DSE)
0 : Interrupt disabled
1 : Interrupt enabled
2 Serial I/O interrupt
enable bit (SIOE)
0 : Interrupt disabled
1 : Interrupt enabled
3 f(XIN)/4096 • SPRITE OSD
interrupt enable bit (CKE)
0 : Interrupt disabled
1 : Interrupt enabled
4 INT2 interrupt enable
bit (IN2E)
0 : Interrupt disabled
1 : Interrupt enabled
5 Multi-master I²C-BUS interface 0 : Interrupt disabled
interrupt enable bit (IICE)
1 : Interrupt enabled
6 Timer 5 • 6 interrupt
enable bit (TM56E)
0 : Interrupt disabled
1 : Interrupt enabled
7 Timer 5 • 6 interrupt
switch bit (TM56S)
0 : Timer 5
1 : Timer 6
After reset R W
0 RW
0 RW
0 RW
0 RW
0 RW
0 RW
0 RW
0 RW
Fig. 12.3.5 Interrupt Control Register 2
24
Rev. 1.0