PIC18F4550-IP Datasheet, PDF (72/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
TABLE 5-2: REGISTER FILE SUMMARY (CONTINUED)
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page
OSCCON
IDLEN
IRCF2
IRCF1
IRCF0
OSTS
IOFS
SCS1
SCS0 0100 q000 54, 33
HLVDCON
VDIRMAG
—
IRVST
HLVDEN
HLVDL3
HLVDL2
HLVDL1
HLVDL0 0-00 0101 54, 285
WDTCON
—
—
—
—
—
—
—
SWDTEN --- ---0 54, 304
RCON
IPEN
SBOREN⁽²⁾
—
RI
TO
PD
POR
BOR
0q-1 11q0 54, 46
TMR1H
Timer1 Register High Byte
xxxx xxxx 54, 136
TMR1L
Timer1 Register Low Byte
xxxx xxxx 54, 136
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0000 0000 54, 131
TMR2
Timer2 Register
0000 0000 54, 138
PR2
Timer2 Period Register
1111 1111 54, 138
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 54, 137
SSPBUF
SSPADD
MSSP Receive Buffer/Transmit Register
MSSP Address Register in I²C™ Slave mode. MSSP Baud Rate Reload Register in I²C™ Master mode.
xxxx xxxx 54, 198,
207
0000 0000 54, 207
SSPSTAT
SMP
CKE
D/A
P
S
R/W
UA
BF
0000 0000 54, 198,
208
SSPCON1
WCOL
SSPOV
SSPEN
CKP
SSPM3
SSPM2
SSPM1
SSPM0 0000 0000 54, 199,
209
SSPCON2
GCEN
ACKSTAT ACKDT/ ACKEN/
RCEN/
PEN/
RSEN/
ADMSK5⁽⁷⁾ ADMSK4⁽⁷⁾ ADMSK3⁽⁷⁾ ADMSK2⁽⁷⁾ ADMSK1⁽⁷⁾
SEN
0000 0000 54, 210
ADRESH
A/D Result Register High Byte
xxxx xxxx 54, 274
ADRESL
A/D Result Register Low Byte
xxxx xxxx 54, 274
ADCON0
—
—
CHS3
CHS2
CHS1
CHS0 GO/DONE ADON --00 0000 54, 265
ADCON1
—
—
VCFG1
VCFG0
PCFG3
PCFG2
PCFG1
PCFG0 --00 0qqq 54, 266
ADCON2
ADFM
—
ACQT2
ACQT1
ACQT0
ADCS2
ADCS1
ADCS0 0-00 0000 54, 267
CCPR1H
Capture/Compare/PWM Register 1 High Byte
xxxx xxxx 55, 144
CCPR1L
CCP1CON
Capture/Compare/PWM Register 1 Low Byte
P1M1⁽³⁾
P1M0⁽³⁾
DC1B1
DC1B0
CCP1M3
CCP1M2
CCP1M1
CCP1M0
xxxx xxxx 55, 144
0000 0000 55, 143,
151
CCPR2H
Capture/Compare/PWM Register 2 High Byte
xxxx xxxx 55, 144
CCPR2L
Capture/Compare/PWM Register 2 Low Byte
xxxx xxxx 55, 144
CCP2CON
—
—
DC2B1
DC2B0
CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 55, 143
BAUDCON
ECCP1DEL
ECCP1AS
ABDOVF
PRSEN
ECCPASE
RCIDL
PDC6⁽³⁾
ECCPAS2
RXDTP
PDC5⁽³⁾
ECCPAS1
TXCKP
PDC4⁽³⁾
ECCPAS0
BRG16
PDC3⁽³⁾
PSSAC1
—
PDC2⁽³⁾
PSSAC0
WUE
PDC1⁽³⁾
PSSBD1⁽³⁾
ABDEN
PDC0⁽³⁾
PSSBD0⁽³⁾
0100 0-00
0000 0000
0000 0000
55, 246
55, 160
55, 161
CVRCON
CVREN
CVROE
CVRR
CVRSS
CVR3
CVR2
CVR1
CVR0 0000 0000 55, 281
CMCON
C2OUT
C1OUT
C2INV
C1INV
CIS
CM2
CM1
CM0
0000 0111 55, 275
TMR3H
Timer3 Register High Byte
xxxx xxxx 55, 141
TMR3L
Timer3 Register Low Byte
xxxx xxxx 55, 141
T3CON
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 55, 139
SPBRGH
EUSART Baud Rate Generator Register High Byte
0000 0000 55, 247
SPBRG
EUSART Baud Rate Generator Register Low Byte
0000 0000 55, 247
RCREG
EUSART Receive Register
0000 0000 55, 256
TXREG
EUSART Transmit Register
0000 0000 55, 253
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D 0000 0010 55, 244
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D 0000 000x 55, 245
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
I²C™ Slave mode only.
DS39632E-page 70
© 2009 Microchip Technology Inc.