PIC18F4550-IP Datasheet, PDF (116/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
TABLE 10-1: PORTA I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O Type
Description
RA0/AN0
RA0
0
OUT
DIG LATA<0> data output; not affected by analog input.
1
IN
TTL PORTA<0> data input; disabled when analog input enabled.
AN0
1
IN
ANA A/D Input Channel 0 and Comparator C1- input. Default configuration
on POR; does not affect digital output.
RA1/AN1
RA1
0
OUT
DIG LATA<1> data output; not affected by analog input.
1
IN
TTL PORTA<1> data input; reads ‘0’ on POR.
AN1
1
IN
ANA A/D Input Channel 1 and Comparator C2- input. Default configuration
on POR; does not affect digital output.
RA2/AN2/
VREF-/CVREF
RA2
0
OUT
DIG LATA<2> data output; not affected by analog input. Disabled when
CVREF output enabled.
1
IN
TTL PORTA<2> data input. Disabled when analog functions enabled;
disabled when CVREF output enabled.
AN2
1
IN
ANA A/D Input Channel 2 and Comparator C2+ input. Default configuration
on POR; not affected by analog output.
VREF-
1
IN
ANA A/D and comparator voltage reference low input.
CVREF
x
OUT ANA Comparator voltage reference output. Enabling this feature disables
digital I/O.
RA3/AN3/
VREF+
RA3
0
OUT
DIG LATA<3> data output; not affected by analog input.
1
IN
TTL PORTA<3> data input; disabled when analog input enabled.
AN3
1
IN
ANA A/D Input Channel 3 and Comparator C1+ input. Default configuration
on POR.
VREF+
1
IN
ANA A/D and comparator voltage reference high input.
RA4/T0CKI/
RA4
C1OUT/RCV
0
OUT
DIG LATA<4> data output; not affected by analog input.
1
IN
ST PORTA<4> data input; disabled when analog input enabled.
T0CKI
1
IN
ST Timer0 clock input.
C1OUT
0
OUT
DIG Comparator 1 output; takes priority over port data.
RCV
x
IN
TTL External USB transceiver RCV input.
RA5/AN4/SS/
RA5
HLVDIN/C2OUT
0
OUT
DIG LATA<5> data output; not affected by analog input.
1
IN
TTL PORTA<5> data input; disabled when analog input enabled.
AN4
1
IN
ANA A/D Input Channel 4. Default configuration on POR.
SS
1
IN
TTL Slave select input for MSSP module.
HLVDIN
1
IN
ANA High/Low-Voltage Detect external trip point input.
C2OUT
0
OUT
DIG Comparator 2 output; takes priority over port data.
OSC2/CLKO/
RA6
OSC2
CLKO
x
OUT ANA Main oscillator feedback output connection (all XT and HS modes).
x
OUT
DIG System cycle clock output (FOSC/4); available in EC, ECPLL and
INTCKO modes.
RA6
0
OUT
DIG LATA<6> data output. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
1
IN
TTL PORTA<6> data input. Available only in ECIO, ECPIO and INTIO
modes; otherwise, reads as ‘0’.
Legend: OUT = Output, IN = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
DS39632E-page 114
© 2009 Microchip Technology Inc.