PIC18F4550-IP Datasheet, PDF (166/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
TABLE 16-3: REGISTERS ASSOCIATED WITH ECCP MODULE AND TIMER1 TO TIMER3
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on page
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
53
RCON
IPEN SBOREN⁽¹⁾
—
RI
TO
PD
POR
BOR
54
IPR1
SPPIP⁽²⁾
ADIP
RCIP
TXIP
SSPIP
CCP1IP TMR2IP TMR1IP
56
PIR1
SPPIF⁽²⁾
ADIF
RCIF
TXIF
SSPIF
CCP1IF TMR2IF TMR1IF
56
PIE1
SPPIE⁽²⁾
ADIE
RCIE
TXIE
SSPIE
CCP1IE TMR2IE TMR1IE
56
IPR2
OSCFIP
CMIP
USBIP
EEIP
BCLIP
HLVDIP TMR3IP CCP2IP
56
PIR2
OSCFIF
CMIF
USBIF
EEIF
BCLIF
HLVDIF TMR3IF CCP2IF
56
PIE2
OSCFIE
CMIE
USBIE
EEIE
BCLIE
HLVDIE TMR3IE CCP2IE
56
TRISB
TRISB7 TRISB6
TRISB5
TRISB4
TRISB3
TRISB2
TRISB1
TRISB0
56
TRISC
TRISC7 TRISC6
—
—
—
TRISC2 TRISC1 TRISC0
56
TRISD⁽²⁾
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
56
TMR1L
Timer1 Register Low Byte
54
TMR1H
Timer1 Register High Byte
54
T1CON
RD16
T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
54
TMR2
Timer2 Module Register
54
T2CON
—
T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0
54
PR2
Timer2 Period Register
54
TMR3L
Timer3 Register Low Byte
55
TMR3H
Timer3 Register High Byte
55
T3CON
RD16
T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON
55
CCPR1L
Capture/Compare/PWM Register 1 (LSB)
55
CCPR1H Capture/Compare/PWM Register 1 (MSB)
55
CCP1CON
P1M1⁽²⁾
P1M0⁽²⁾
DC1B1
DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0
55
ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1⁽²⁾ PSSBD0⁽²⁾
55
ECCP1DEL PRSEN PDC6⁽²⁾
PDC5⁽²⁾
PDC4⁽²⁾
PDC3⁽²⁾
PDC2⁽²⁾
PDC1⁽²⁾
PDC0⁽²⁾
55
Legend:
Note 1:
2:
— = unimplemented, read as ‘0’. Shaded cells are not used during ECCP operation.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These bits or registers are unimplemented in 28-pin devices; always maintain these bits clear.
DS39632E-page 164
© 2009 Microchip Technology Inc.