PIC18F4550-IP Datasheet, PDF (397/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
FIGURE 28-13: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)
SS
SCK
(CKP = 0)
70
71
72
83
78
79
SCK
(CKP = 1)
80
79
78
SDO
MSb
bit 6 - - - - - -1
LSb
SDI
Note:
MSb In
74
73
75, 76
bit 6 - - - -1
Refer to Figure 28-4 for load conditions.
77
LSb In
TABLE 28-17: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0)
Param
No.
Symbol
Characteristic
Min
Max Units Conditions
70
TssL2scH, SS ↓ to SCK ↓ or SCK ↑ Input
TssL2scL
3 TCY
—
71
TscH
71A
SCK Input High Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
72
TscL
72A
SCK Input Low Time
(Slave mode)
Continuous
Single Byte
1.25 TCY + 30 —
40
—
73
TdiV2scH, Setup Time of SDI Data Input to SCK Edge
TdiV2scL
20
—
73A Tb2b
Last Clock Edge of Byte 1 to the First Clock Edge of Byte 2 1.5 TCY + 40 —
74
TscH2diL, Hold Time of SDI Data Input to SCK Edge
TscL2diL
35
—
75
TdoR
SDO Data Output Rise Time
PIC18FXXXX
—
25
PIC18LFXXXX
—
45
76
TdoF
SDO Data Output Fall Time
—
25
77
TssH2doZ SS ↑ to SDO Output High-Impedance
10
50
78
TscR
SCK Output Rise Time (Master mode) PIC18FXXXX
—
25
PIC18LFXXXX
—
45
79
TscF
SCK Output Fall Time (Master mode)
—
25
80
TscH2doV, SDO Data Output Valid after SCK Edge PIC18FXXXX
—
50
TscL2doV
PIC18LFXXXX
—
100
83
TscH2ssH, SS ↑ after SCK edge
TscL2ssH
1.5 TCY + 40 —
Note 1: Requires the use of Parameter 73A.
2: Only if Parameter 71A and 72A are used.
ns
ns
ns (Note 1)
ns
ns (Note 1)
ns
ns (Note 2)
ns
ns
ns VDD = 2.0V
ns
ns
ns
ns VDD = 2.0V
ns
ns
ns VDD = 2.0V
ns
© 2009 Microchip Technology Inc.
DS39632E-page 395