PIC18F4550-IP Datasheet, PDF (425/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
INDEX
A
A/D ................................................................................... 265
Acquisition Requirements ........................................ 270
ADCON0 Register .................................................... 265
ADCON1 Register .................................................... 265
ADCON2 Register .................................................... 265
ADRESH Register ............................................ 265, 268
ADRESL Register .................................................... 265
Analog Port Pins, Configuring .................................. 272
Associated Registers ............................................... 274
Configuring the Module ............................................ 269
Conversion Clock (TAD) ........................................... 271
Conversion Requirements ....................................... 405
Conversion Status (GO/DONE Bit) .......................... 268
Conversions ............................................................. 273
Converter Characteristics ........................................ 404
Converter Interrupt, Configuring .............................. 269
Discharge ................................................................. 273
Operation in Power-Managed Modes ...................... 272
Selecting and Configuring Acquisition Time ............ 271
Special Event Trigger (CCP2) .................................. 274
Special Event Trigger (ECCP) ................................. 152
Use of the CCP2 Trigger .......................................... 274
Absolute Maximum Ratings ............................................. 367
AC (Timing) Characteristics ............................................. 385
Load Conditions for Device Timing
Specifications ................................................... 386
Parameter Symbology ............................................. 385
Temperature and Voltage Specifications ................. 386
Timing Conditions .................................................... 386
AC Characteristics
Internal RC Accuracy ............................................... 388
Access Bank
Mapping with Indexed Literal Offset Mode ................. 79
ACKSTAT ........................................................................ 232
ACKSTAT Status Flag ..................................................... 232
ADCON0 Register ............................................................ 265
GO/DONE Bit ........................................................... 268
ADCON1 Register ............................................................ 265
ADCON2 Register ............................................................ 265
ADDFSR .......................................................................... 356
ADDLW ............................................................................ 319
ADDULNK ........................................................................ 356
ADDWF ............................................................................ 319
ADDWFC ......................................................................... 320
ADRESH Register ............................................................ 265
ADRESL Register .................................................... 265, 268
Analog-to-Digital Converter. See A/D.
and BSR ............................................................................. 79
ANDLW ............................................................................ 320
ANDWF ............................................................................ 321
Assembler
MPASM Assembler .................................................. 364
B
Baud Rate Generator ....................................................... 228
BC .................................................................................... 321
BCF .................................................................................. 322
BF .................................................................................... 232
BF Status Flag ................................................................. 232
Block Diagrams
A/D ........................................................................... 268
Analog Input Model .................................................. 269
Baud Rate Generator .............................................. 228
Capture Mode Operation ......................................... 145
Comparator Analog Input Model .............................. 279
Comparator I/O Operating Modes ........................... 276
Comparator Output .................................................. 278
Comparator Voltage Reference ............................... 282
Comparator Voltage Reference
Output Buffer Example .................................... 283
Compare Mode Operation ....................................... 146
Device Clock .............................................................. 24
Enhanced PWM ....................................................... 153
EUSART Receive .................................................... 257
EUSART Transmit ................................................... 254
External Power-on Reset Circuit
(Slow VDD Power-up) ........................................ 47
Fail-Safe Clock Monitor ........................................... 306
Generic I/O Port ....................................................... 113
High/Low-Voltage Detect with External Input .......... 286
Interrupt Logic .......................................................... 100
MSSP (I²C Master Mode) ........................................ 226
MSSP (I²C Mode) .................................................... 207
MSSP (SPI Mode) ................................................... 197
On-Chip Reset Circuit ................................................ 45
PIC18F2455/2550 ..................................................... 10
PIC18F4455/4550 ..................................................... 11
PLL (HS Mode) .......................................................... 27
PWM Operation (Simplified) .................................... 148
Reads from Flash Program Memory ......................... 85
Single Comparator ................................................... 277
SPP Data Path ........................................................ 191
Table Read Operation ............................................... 81
Table Write Operation ............................................... 82
Table Writes to Flash Program Memory .................... 87
Timer0 in 16-Bit Mode ............................................. 128
Timer0 in 8-Bit Mode ............................................... 128
Timer1 ..................................................................... 132
Timer1 (16-Bit Read/Write Mode) ............................ 132
Timer2 ..................................................................... 138
Timer3 ..................................................................... 140
Timer3 (16-Bit Read/Write Mode) ............................ 140
USB Interrupt Logic ................................................. 180
USB Peripheral and Options ................................... 165
Watchdog Timer ...................................................... 303
BN .................................................................................... 322
BNC ................................................................................. 323
BNN ................................................................................. 323
BNOV .............................................................................. 324
BNZ ................................................................................. 324
BOR. See Brown-out Reset.
BOV ................................................................................. 327
BRA ................................................................................. 325
Break Character (12-Bit) Transmit and Receive .............. 259
BRG. See Baud Rate Generator.
Brown-out Reset (BOR) ..................................................... 48
Detecting ................................................................... 48
Disabling in Sleep Mode ............................................ 48
Software Enabled ...................................................... 48
BSF .................................................................................. 325
BTFSC ............................................................................. 326
BTFSS ............................................................................. 326
BTG ................................................................................. 327
BZ .................................................................................... 328
© 2009 Microchip Technology Inc.
DS39632E-page 423