PIC18F4550-IP Datasheet, PDF (310/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
25.5 Program Verification and
Code Protection
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PIC^® devices.
The user program memory is divided into five blocks.
One of these is a boot block of 2 Kbytes. The remainder
of the memory is divided into four blocks on binary
boundaries.
Each of the five blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 25-5 shows the program memory organization
for 24 and 32-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 25-3.
FIGURE 25-5:
CODE-PROTECTED PROGRAM MEMORY
MEMORY SIZE/DEVICE
24 Kbytes
Boot Block
Block 0
Block 1
Block 2
Unimplemented
Read ‘0’s
32 Kbytes
Boot Block
Block 0
Block 1
Block 2
Block 3
Address
Range
000000h
0007FFh
000800h
001FFFh
002000h
003FFFh
004000h
005FFFh
006000h
007FFFh
008000h
Block Code Protection
Controlled By:
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Unimplemented
Read ‘0’s
Unimplemented
Read ‘0’s
(Unimplemented Memory Space)
1FFFFFh
TABLE 25-3: SUMMARY OF CODE PROTECTION REGISTERS
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
300008h CONFIG5L —
—
—
—
CP3⁽¹⁾
300009h CONFIG5H CPD
CPB
—
30000Ah CONFIG6L —
—
—
—
—
—
WRT3⁽¹⁾
30000Bh
30000Ch
CONFIG6H WRTD
CONFIG7L —
WRTB
—
WRTC
—
—
—
—
EBTR3⁽¹⁾
30000Dh CONFIG7H —
EBTRB
—
—
—
Legend: Shaded cells are unimplemented.
Note 1: Unimplemented in PIC18FX455 devices; maintain this bit set.
Bit 2
CP2
—
WRT2
—
EBTR2
—
Bit 1
CP1
—
WRT1
—
EBTR1
—
Bit 0
CP0
—
WRT0
—
EBTR0
—
DS39632E-page 308
© 2009 Microchip Technology Inc.