PIC18F4550-IP Datasheet, PDF (211/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
REGISTER 19-4: SSPCON1: MSSP CONTROL REGISTER 1 (I²C™ MODE)
R/W-0
WCOL
bit 7
R/W-0
SSPOV
R/W-0
SSPEN
R/W-0
CKP
R/W-0
SSPM3
R/W-0
SSPM2
R/W-0
SSPM1
R/W-0
SSPM0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3-0
WCOL: Write Collision Detect bit
In Master Transmit mode:
1 = A write to the SSPBUF register was attempted while the I²C conditions were not valid for a
transmission to be started (must be cleared in software)
0 = No collision
In Slave Transmit mode:
1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in
software)
0 = No collision
In Receive mode (Master or Slave modes):
This is a “don’t care” bit.
SSPOV: Receive Overflow Indicator bit
In Receive mode:
1 = A byte is received while the SSPBUF register is still holding the previous byte (must be cleared in
software)
0 = No overflow
In Transmit mode:
This is a “don’t care” bit in Transmit mode.
SSPEN: Master Synchronous Serial Port Enable bit
1 = Enables the serial port and configures the SDA and SCL pins as the serial port pins⁽¹⁾
0 = Disables serial port and configures these pins as I/O port pins⁽¹⁾
CKP: SCK Release Control bit
In Slave mode:
1 = Release clock
0 = Holds clock low (clock stretch), used to ensure data setup time
In Master mode:
Unused in this mode.
SSPM3:SSPM0: Master Synchronous Serial Port Mode Select bits
1111 = I²C Slave mode, 10-bit address with Start and Stop bit interrupts enabled⁽²⁾
1110 = I²C Slave mode, 7-bit address with Start and Stop bit interrupts enabled⁽²⁾
1011 = I²C Firmware Controlled Master mode (slave Idle)⁽²⁾
1000 = I²C Master mode, clock = FOSC/(4 * (SSPADD + 1))^(2,3)
0111 = I²C Slave mode, 10-bit address⁽²⁾
0110 = I²C Slave mode, 7-bit address⁽²⁾
Note 1:
2:
3:
When enabled, the SDA and SCL pins must be properly configured as input or output.
Bit combinations not specifically listed here are either reserved or implemented in SPI mode only.
Guideline only; exact baud rate slightly dependent upon circuit conditions, but the highest clock rate
should not exceed this formula. SSPADD values of ‘0’ and ‘1’ are not supported.
© 2009 Microchip Technology Inc.
DS39632E-page 209