PIC18F4550-IP Datasheet, PDF (71/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
TABLE 5-2: REGISTER FILE SUMMARY
File Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on Details
POR, BOR on page
TOSU
—
—
—
Top-of-Stack Upper Byte (TOS<20:16>)
---0 0000 53, 60
TOSH
Top-of-Stack High Byte (TOS<15:8>)
0000 0000 53, 60
TOSL
Top-of-Stack Low Byte (TOS<7:0>)
0000 0000 53, 60
STKPTR
STKFUL STKUNF
—
SP4
SP3
SP2
SP1
SP0
00-0 0000 53, 61
PCLATU
—
—
—
Holding Register for PC<20:16>
---0 0000 53, 60
PCLATH
Holding Register for PC<15:8>
0000 0000 53, 60
PCL
TBLPTRU
PC Low Byte (PC<7:0>)
—
—
bit 21⁽¹⁾ Program Memory Table Pointer Upper Byte (TBLPTR<20:16>)
0000 0000 53, 60
--00 0000 53, 84
TBLPTRH Program Memory Table Pointer High Byte (TBLPTR<15:8>)
0000 0000 53, 84
TBLPTRL Program Memory Table Pointer Low Byte (TBLPTR<7:0>)
0000 0000 53, 84
TABLAT
Program Memory Table Latch
0000 0000 53, 84
PRODH
Product Register High Byte
xxxx xxxx 53, 97
PRODL
Product Register Low Byte
xxxx xxxx 53, 97
INTCON
GIE/GIEH PEIE/GIEL TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF 0000 000x 53, 101
INTCON2
RBPU
INTEDG0 INTEDG1 INTEDG2
—
TMR0IP
—
RBIP 1111 -1-1 53, 102
INTCON3
INT2IP
INT1IP
—
INT2IE
INT1IE
—
INT2IF
INT1IF 11-0 0-00 53, 103
INDF0
Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register)
N/A
53, 75
POSTINC0 Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register)
N/A
53, 76
POSTDEC0 Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register)
N/A
53, 76
PREINC0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register)
N/A
53, 76
PLUSW0
Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) –
value of FSR0 offset by W
N/A
53, 76
FSR0H
—
—
—
—
Indirect Data Memory Address Pointer 0 High Byte
---- 0000 53, 75
FSR0L
Indirect Data Memory Address Pointer 0 Low Byte
xxxx xxxx 53, 75
WREG
Working Register
xxxx xxxx 53
INDF1
Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register)
N/A
53, 75
POSTINC1 Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register)
N/A
53, 76
POSTDEC1 Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register)
N/A
53, 76
PREINC1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register)
N/A
53, 76
PLUSW1
Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) –
value of FSR1 offset by W
N/A
53, 76
FSR1H
—
—
—
—
Indirect Data Memory Address Pointer 1 High Byte
---- 0000 53, 75
FSR1L
Indirect Data Memory Address Pointer 1 Low Byte
xxxx xxxx 53, 75
BSR
—
—
—
—
Bank Select Register
---- 0000 54, 65
INDF2
Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register)
N/A
54, 75
POSTINC2 Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register)
N/A
54, 76
POSTDEC2 Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register)
N/A
54, 76
PREINC2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register)
N/A
54, 76
PLUSW2
Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) –
value of FSR2 offset by W
N/A
54, 76
FSR2H
—
—
—
—
Indirect Data Memory Address Pointer 2 High Byte
---- 0000 54, 75
FSR2L
Indirect Data Memory Address Pointer 2 Low Byte
xxxx xxxx 54, 75
STATUS
—
—
—
N
OV
Z
DC
C
---x xxxx 54, 73
TMR0H
Timer0 Register High Byte
0000 0000 54, 129
TMR0L
Timer0 Register Low Byte
xxxx xxxx 54, 129
T0CON
TMR0ON T08BIT
T0CS
T0SE
PSA
T0PS2
T0PS1
T0PS0 1111 1111 54, 127
Legend:
Note 1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition. Shaded cells are unimplemented, read as ‘0’.
Bit 21 of the TBLPTRU allows access to the device Configuration bits.
The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’.
These registers and/or bits are not implemented on 28-pin devices and are read as ‘0’. Reset values are shown for 40/44-pin devices;
individual unimplemented bits should be interpreted as ‘-’.
RA6 is configured as a port pin based on various primary oscillator modes. When the port pin is disabled, all of the associated bits read ‘0’.
RE3 is only available as a port pin when the MCLRE Configuration bit is clear; otherwise, the bit reads as ‘0’.
RC5 and RC4 are only available as port pins when the USB module is disabled (UCON<3> = 0).
I²C™ Slave mode only.
© 2009 Microchip Technology Inc.
DS39632E-page 69