PIC18F4550-IP Datasheet, PDF (189/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
17.7 Streaming Parallel Port
The Streaming Parallel Port (SPP) is an alternate route
option for data besides USB RAM. Using the SPP, an
endpoint can be configured to send data to or receive
data directly from external hardware.
This methodology presents design possibilities where
the microcontroller acts as a data manager, allowing
the SPP to pass large blocks of data without the micro-
controller actually processing it. An application
example might include a data acquisition system,
where data is streamed from an external FIFO through
USB to the host computer. In this case, endpoint
control is managed by the microcontroller and raw data
movement is processed externally.
The SPP is enabled as a USB endpoint port through
the associated endpoint buffer descriptor. The endpoint
must be enabled as follows:
1. Set BDnADRL:BDnADRH to point to FFFFh.
2. Set the KEN bit (BDnSTAT<5>) to let SIE keep
control of the buffer.
3. Set the INCDIS bit (BDnSTAT<4>) to disable
automatic address increment.
Refer to Section 18.0 “Streaming Parallel Port” for
more information about the SPP.
Note 1: If an endpoint is configured to use the
SPP, the SPP module must also be
configured to use the USB module.
Otherwise, unexpected operation may
occur.
2: In addition, if an endpoint is configured to
use the SPP, the data transfer type of that
endpoint must be isochronous only.
17.8 Oscillator
The USB module has specific clock requirements. For
full-speed operation, the clock source must be 48 MHz.
Even so, the microcontroller core and other peripherals
are not required to run at that clock speed or even from
the same clock source. Available clocking options are
described in detail in Section 2.3 “Oscillator Settings
for USB”.
TABLE 17-6: REGISTERS ASSOCIATED WITH USB MODULE OPERATION⁽¹⁾
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Details on
page
INTCON
IPR2
PIR2
Legend:
Note 1:
GIE/GIEH PEIE/GIEL TMR0IE INT0IE
RBIE
TMR0IF
INT0IF
RBIF
53
OSCFIP
CMIP
USBIP
EEIP
BCLIP
HLVDIP TMR3IP CCP2IP
56
OSCFIF
CMIF
USBIF
EEIF
BCLIF
HLVDIF TMR3IF CCP2IF
56
— = unimplemented, read as ‘0’. Shaded cells are not used by the USB module.
This table includes only those hardware mapped SFRs located in Bank 15 of the data memory space. The Buffer
Descriptor registers, which are mapped into Bank 4 and are not true SFRs, are listed separately in Table 17-5.
© 2009 Microchip Technology Inc.
DS39632E-page 187