PIC18F4550-IP Datasheet, PDF (202/438 Pages) Microchip Technology – 28/40/44-Pin, High-Performance, Enhanced Flash, USB Microcontrollers with nanoWatt Technology

PIC18F2455/2550/4455/4550
19.3.2 OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCK is the clock output)
• Slave mode (SCK is the clock input)
• Clock Polarity (Idle state of SCK)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCK)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
The MSSP module consists of a transmit/receive shift
register (SSPSR) and a buffer register (SSPBUF). The
SSPSR shifts the data in and out of the device, MSb
first. The SSPBUF holds the data that was written to the
SSPSR until the received data is ready. Once the eight
bits of data have been received, that byte is moved to
the SSPBUF register. Then, the Buffer Full detect bit,
BF (SSPSTAT<0>) and the interrupt flag bit, SSPIF, are
set. This double-buffering of the received data
(SSPBUF) allows the next byte to start reception before
reading the data that was just received. Any write to the
SSPBUF register during transmission/reception of data
will be ignored and the Write Collision detect bit, WCOL
(SSPCON1<7>), will be set. User software must clear
the WCOL bit so that it can be determined if the follow-
ing write(s) to the SSPBUF register completed
successfully.
Note:
When the application software is expect-
ing to receive valid data, the SSPBUF
should be read before the next byte of
data to transfer is written to the SSPBUF.
Application software should follow this
process even when the current contents of
SSPBUF are not important.
The Buffer Full bit, BF (SSPSTAT<0>), indicates when
SSPBUF has been loaded with the received data
(transmission is complete). When the SSPBUF is read,
the BF bit is cleared. This data may be irrelevant if the
SPI is only a transmitter. Generally, the MSSP interrupt
is used to determine when the transmission/reception
has completed. If the interrupt method is not going to
be used, then software polling can be done to ensure
that a write collision does not occur. Example 19-1
shows the loading of the SSPBUF (SSPSR) for data
transmission.
The SSPSR is not directly readable or writable and can
only be accessed by addressing the SSPBUF register.
Additionally, the MSSP Status register (SSPSTAT)
indicates the various status conditions.
Note:
The SSPBUF register cannot be used with
read-modify-write instructions, such as
BCF, BTFSC and COMF.
EXAMPLE 19-1: LOADING THE SSPBUF (SSPSR) REGISTER
TransmitSPI:
BCF
PIR1, SSPIF
MOVF
MOVWF
MOVF
MOVWF
SSPBUF, W
RXDATA
TXDATA, W
SSPBUF
;Make sure interrupt flag is clear (may have been set from previous
transmission).
;Perform read, even if the data in SSPBUF is not important
;Save previously received byte in user RAM, if the data is meaningful
;WREG = Contents of TXDATA (user data to send)
;Load data to send into transmit buffer
WaitComplete:
BTFSS PIR1, SSPIF
BRA
WaitComplete
;Loop until data has finished transmitting
;Interrupt flag set when transmit is complete
DS39632E-page 200
© 2009 Microchip Technology Inc.