BBT3420 Datasheet, PDF (9/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
the DSKW_SM_EN bit is set to 0, channel deskew can still
be enabled by setting CAL_EN, but the deskew action will be
carried out without hysteresis.
The user has the option to disable trunking, or enable
trunking across 4 channels, under control of the PSYNC pin
(Table 4-6) and the RCLKMODE bits in the MDIO Registers
at address 18’h in Clause 22 format and/or C000’h in Clause
45 format (see Table 3-21 and/or Table 3-32). In trunking
mode, the channels may have phase differences, but they
are expected to be frequency synchronous. In non-trunking
mode, each received serial stream need only be within
±100ppm of 3.125Gbps (or 1.56125) Gbps. Note that
trunking mode is only possible if 8b/10b Coding is activated,
and all channels have the same half-rate setting (Table 3-
30).
3.8.2 CLOCK COMPENSATION
In addition to deskew, the Receive FIFO also compensates
for clock differences. Since the received serial stream can,
under worst-case conditions, be off by up to ±200ppm from
the local clock domain (both can be up to ±100ppm from
nominal), the received data must be adjusted to the local
frequency. The received data can be aligned in one of three
ways, under control of the PSYNC pin (Table 4-6) and the
RCLKMODE bits in MDIO Register 18’h in Clause 22 format
and/or C000’h in Clause 45 format (see Table 3-21 and/or
Table 3-32):
1. Local Reference Clock (trunking mode)
2. Recovered Clock for each channel (non-trunking mode)
3. Recovered Clock for Channel A (trunking mode)
Another 8 bytes of RXFIFO are dedicated for clock
compensation. The FIFOs achieve clock tolerance by
identifying any of the IDLE patterns in the XAUI input (/K/, /A/
or /R/ as defined by the IEEE 802.3ae-2002 standard) in the
received data and then adding or dropping IDLEs as
needed. The Receive FIFO does not store the actual IDLE
sequences received but generates the number of IDLEs
needed to compensate for clock tolerance differences. See
also Table 3-3 on page 8.
3.9 Error Recovery
Errors in the high-speed links can be separated into two
types, Loss of Signal and Coding Error violations. These are
handled differently by the Error Recovery system in the
BBT3420.
3.10 Disparity Error & Coding Violation
3.10.1 XGMII 8 BIT MODE
If 8b/10b encoding/decoding is turned on, the BBT3420
expects to receive a properly encoded serial bit stream. If
the received data contains an error, the transceiver will
report it as described below:
The received bits 0-7 represent the 8b/10b decoded value,
bit 8 represents the K value and bit 9 indicates a disparity
error or code error. In the event of a disparity error, the
decoded value is passed to the parallel output [8..0], and bit
9 is asserted to indicate the error. If it is a coding error, the
decoded value presented is a programmable error byte
(default=K30.7). Therefore the value for bit 0-8 is
1,1111,1110’b. Bit 9 is asserted to indicate the error.
This transceiver does not support the even/odd character
mode specific to 1000Base-X operations. Byte alignment
with comma is achieved with a 10-bit period. As a result, a
comma received at any odd or even byte location, but at the
proper byte boundary, will not cause any byte realignment.
3.10.2 10-BIT MODE
If the 8b/10b Codec is inactive, disparity error and coding
violation errors do not apply. System designers must ensure
that the data stream is DC-balanced and contains sufficient
transition density for proper operation, including
synchronization. The required density depends on the
frequency difference between the received data and the
local reference clock, and the incoming signal jitter tolerance
requirement. For a frequency difference of ±100ppm, and a
transition-free data pattern of 500 successive 1’s or 0’s, the
total build-up of CDR timing error is 0.1 UI. If this pattern is
followed by a pattern of normal density, the reduction of jitter
tolerance will usually be acceptable, though if such long no-
transition patterns are common, the jitter buildup could be
cumulative. In a fully synchronous system, where there are
no consistent frequency differences, these effects are of
course reduced.
3.10.3 OUTPUT SELECT – PARALLEL LOOPBACK
In normal mode, the serial input data RX[A..D]P/N data will
be placed on the parallel receive outputs RD[A..D][9..0].
When parallel loopback is activated, the internal parallel
output is routed to the parallel input (including clock) for
every channel. The RD[A..D][9..0] pins may be disabled if
desired, whether in parallel output mode or not, by using the
IPON bit of the MDIO Register at address 011’h (Clause 22
see Table 3-16) and/or address C001’h (Clause 45, see
Table 3-33).
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