BBT3420 Datasheet, PDF (15/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
BIT
15:8
7:6
5:4
3
2:0
TABLE 3-15. MISCELLANEOUS CONTROL REGISTER 1 (CLAUSE 22)
MII REGISTER 16, ADDRESS = 10’h
NAME
SETTING
DEFAULT R/W
DESCRIPTION
Reserved
CDET[1:0]
Bit 7 controls positive comma detection, 11’b
Bit 6 controls negative comma detection
0’b=disable
1’b=enable
R/W
Comma Detect Select. These bits enable detection of
positive, negative, or both positive and negative
disparities of comma, or disable detection of either.
Reserved
TRANS_EN 1=enable
0=disable
0’b
R/W
Enables transceiver to translate an "IDLE" pattern in the
XGMII data (matching the value of register 1B’h) to and
from the XAUI IDLE /K/ comma character or /A/, /K/ & /R/
characters. Overridden by XAUI_EN; see Table 3-28
MF_CTRL
0 = BIST_ERR
1 = LOS
2 = Reserved
3 = RC[A:D]
4 = TXFIFO_ERR
5 = AFIFO_ERR
6 = EFIFO_ERR
00’b
R/W
Control the functions of multi-function pins MF[A-D].
RC[A:D] is recovered clock for each channel [A:D].
BIT
15
14:13
12
11:9
8
7
6
5
4:0
TABLE 3-16. MISCELLANEOUS CONTROL REGISTER 2 (CLAUSE 22)
MII REGISTER 17, ADDRESS = 11’h
NAME
SHRT_BIST
SETTING
DEFAULT
1 = Short BIST Loop pattern 0’b
0 = Long BIST Loop pattern
R/W
R/W
DESCRIPTION
Short is 13458 Byte pattern, Long is 2²³-1 Byte Pattern (plus
9 /K/ "Comma" bytes)
Reserved
BIST_EN
1 = enable BIST Pattern 0’b
0 = disable
R/W
Built In Self Test (BIST) may also be enabled by the BIST_EN
pin or via the JTAG system.
Reserved
IPON
1=enable
0=disable
1’b
R/W
Internal Parallel Output Enable
Reserved
CODECENA 1=enable if CODE pin hi 1’b
0=disable
R/W
Internal 8b/10b Codec enable/disable
SC_TBC
1=source sync
0=source center
0’b
R/W
Timing of incoming Transmit Byte Clock (TBC) to transmit
data
Reserved
15