BBT3420 Datasheet, PDF (26/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
PIN#
P1
A16, B16, T16, U16
C1
B1
C3, D3, P3, R3
D1
U1
P2
TABLE 4-6. MISCELLANEOUS PINS
NAME
TYPE
DESCRIPTION
CODE
Input
(w/pullup)
Encode Enable, When CODE is high, the 8b/10b encoder and decoder are enabled,
provided the CODECENA bit is set, see Table 3-16 and/or Table 3-32. When CODE
is low, the encoder and decoder are disabled, and the Parallel side handles raw 10b
data.
MF[A:D]
Output (MFC Multi-function I/O's, Channels [A:D]. The functions of these pins are enabled via the
and MFD are MDIO. Currently defined functions are:² FIFO_ERR for each channel, for TX, Align
inputs w/pullup and Elasticity FIFOs. LOS (Loss of Signal) for each channel,² RC[A:D]: Recovered
during reset). clock outputs ² COMMA_DET (K28.5 character detected) for each channel, and²
BIST_ERR (Built-In Self Test Pseudo Random Bit Stream Test Status) for each
channel. The default condition for these pins is BIST_ERR. See Table 3-15 and/or
Table 3-33 for further details. MFC and MFD are also used as inputs during reset, to
control the MDIO interface DEVAD value, see Table 3-5.
PSYNC
Input
Channel Synchronization Enable. When PSYNC is high, all transmit data is latched
(w/pulldown) on the rising and falling edges of TCA, all receive data is valid on the rising and falling
edges of RCA.
RSTN
Input
Chip Reset (FIFO Clear)
LPEN(A-D)
Input
Loop Enable, Channels A-D. When high, the serial output for each channel is looped
(w/pulldown) back to its input.
SIG_DET
Output
SIG_DET. This pin is asserted when all four Signal Detectors detect signal levels
above the threshold (see Table 3-28 and/or Table 3-33).
RSVN/
RETIMER
Input
Active Low If low, the BBT3420 acts as a Retimer device, rather than a transceiver
(w/pullup) (SerDes) device.
BISTEN
Input
Built-In Self Test Enable--Active High. When high, enables internal 23-bit PRBS test
(w/pulldown) function.
TABLE 4-7. VOLTAGE SUPPLY AND REFERENCE PINS
PIN#
NAME
TYPE
DESCRIPTION
J17
V_REF
Input
Parallel Side Input Voltage Reference
C2
REFP
Input
When REFP pin is tied to V_DDQ, MF[A-D] are the receiver
complementary clock outputs MFA = RCANMFB = RCBNMFC =
RCCNMFD = RCDN When REFP pin is left as no-connect or tied to
low, MF[A-D] are the multi-function I/O's as defined in Table 4-6
D2
REFN
Input
No Connect Terminal (internal inactive resistor for test purposes.)
J1
RREF
Input
Additional Resistor Terminal (N.C.)
A9, A12, A15, A17, D8, D11, D14, D17, G14, G17,
J14, J16, L14, L17, P8, P11, P14, P17, U9, U12,
U15, U17
V_DDQ
Supply Control and Parallel Input/Output Supply Voltage
D4, D7, E4, H1, H4, J4, K1, K4, N4, P4, P7
VDD
Supply Internal (Core) Supply
A5, A6, A7, C5, C6, F1, F3, G1, G3, L1, L3, M1, VDDA Analog Supply Analog Supply. Should be decoupled from VDD
M3, R5, R6, U5, U6, U7
B9, B12, B15, B17, E5, E6, E7, E8, E11, E14, E17,
H2, H3, H5, H14, H17, J5, K2, K3, K5, K14, K17,
N5, N6, N7, N8, N11, N14, N17, T9, T12, T15, T17
GND
Ground Ground for Core, Control and Parallel Input/Outputs.
A4, B4, B7, C4, C7, E1, E2, E3, F5, G5, L5, M5, GNDA Analog Ground Analog Ground. Should be connected to GND at one point.
N1, N2, N3, R4, R7, T4, T7, U4
F6, F7, F8, F9, F10, F11, F12, G6, G7, G8, G9,
G10, G11,G12, H6, H7, H8, H9, H10, H11, H12,
J6, J7, J8, J9, J10, J11, J12, K6, K7, K8, K9, K10,
K11, K12, L6, L7, L8, L9, L10, L11, L12, M6, M7,
M8, M9, M10, M11, M12
T-GND
Ground
Thermal Grounds. Electrically tied to Ground, but used to improve
thermal transfer to mounting medium (PCB).
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