BBT3420 Datasheet, PDF (37/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

TX[A:D]P/N
BBT3420
t_OCCDS
TX[A:D]P/N
FIGURE 6-13. CHANNEL-TO-CHANNEL DIFFERENTIAL SKEW
Applications Information
DTE XGXS (XGMII-to-XAUI) Setup
One of many applications of the BBT3420 is utilizing it as a
10Gigabit Ethernet DTE XGXS device. The following
discussion focuses on configuring the BBT3420 to operate
as a DTE XGXS device. It also assumes the default register
setting after a hard reset.
The MFC and MFD pins have internal pull-up resistors
(approx. 50kΩ), therefore no external resistor is needed to
configure the BBT3420 to DEVICE ADDRESS 5 (see
Table 3-5). The CODE and PSYNC pins should be pulled HI
(to V_DDQ), and BISTEN and LPENA-D pulled LOW (to
GND); all these pins except PSYNC have internal pulls to
these values.
Some of the default register settings need to be changed, for
XGMII-to-XAUI operation. The register addresses are
described with the Clause 22 address followed by the
Clause 45 address. The default value of the A_ALIGN_DIS
bit of the Symbol and Elasticity Control MII Register
(19’h/C000’h) will cause channel alignment to occur on IDLE
to non-IDLE transitions across all four channels. This can be
changed to channel alignment on /A/ (K28.3) characters by
setting this bit to a zero, to conform to the XAUI
specification. The internal (XGMII) Error character should be
set to 1FE’h by writing FE’h to 16’h/C002’h. The pseudo-
random XAUI IDLE /A/K/R/ generator should be enabled by
setting the AKR_EN bit in register 1D’h/C001’h. To allow
complete regeneration of the Inter Packet Gap (IPG), it is
desirable to set the TRANS_EN bit in register 10’h/C001’h.
For the best XAUI-conforming performance, it is also
advisable to set the PCS_SYNC_EN and DSKW_SM_EN
bits in register 1D’h/C000’h.
All the above listed register settings can be overridden,
effectively forcing the BBT3420 to the desired conditions, by
setting the XAUI_EN bit in register 1D’h/C001’h.
Additional register settings may be desirable in certain
environments. If the incoming XAUI signals have traveled
some distance from their source (or if the source provides a
weak signal), it will usually be advisable to use the equalizer
to improve the signal integrity. Similarly, if the transmitted
XAUI signals are to travel a significant distance, pre-
emphasis may be desirable. Both these can be changed
from their default values (0’h) via register 1C’h/C005’h. It
may also be found desirable to alter the LOS detector
threshold, using register 1D’h/C001’h.
Recommended Analog Power and Ground Plane
Splits
The BBT3420 high-speed analog circuits as well as high-
speed I/O draw power from the analog power (VDDA) and
analog ground GNDA pins/balls (pins or balls will be used
inter-changeably through out this document). In order for the
BBT3420 to achieve best performance, the VDDA and
GNDA shall be kept as “quiet” as possible.
The VDDA voltage requirement of the BBT3420 is 1.8V. The
ripple noise on the VDDA voltage rail shall be as low as
possible for best jitter performance. Therefore, in the layout,
VDDA shall be decoupled from the main supply of 1.8V by
means of a cut out in the power plane. The 1.8V power to
VDDA is supplied through a ferrite bead (capable of 1A is
recommended). The cut out spacing shall be at least 20mil.
A “quiet” analog ground also enhances the jitter performance
of the BBT3420 as well. A similar cut out in the ground plane
is recommended. Analog ground (GNDA) shall be tied to
digital ground (GND) through a ferrite bead (capable of at
least 1A is recommended).
Recommended Power Supply Decoupling
For BBT3420, the decoupling for V_DDA V_DD and V_DDQ must
all be handled individually.
VDDA (1.8V) provides power to the analog circuits as well as
the high speed I/Os. The analog power supply VDDA must
have impedance less than 0.4Ω from around 50kHz to
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