BBT3420 Datasheet, PDF (16/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
BIT
15
14
13
12
11:8
7:4
3
2
1
0
NAME
EQ_DC_D
EQ_DC_C
EQ_DC_B
EQ_DC_A
Reserved
Reserved
RCD_Invert
RCC_Invert
RCB_Invert
RCA_Invert
TABLE 3-17. SPECIAL CONTROL REGISTER
MII REGISTER 18 & 49162, ADDRESSES = 12’h & C00A’h
SETTING
DEFAULT R/W
DESCRIPTION
1=DC offset correction disable. 0’b
0=DC offset correction enable.
R/W Channel D receive differential input DC offset correction
disable/enable.
1=DC offset correction disable. 0’b
0=DC offset correction enable.
R/W Channel C receive differential input DC offset correction
disable/enable.
1=DC offset correction disable. 0’b
0=DC offset correction enable.
R/W Channel B receive differential input DC offset correction
disable/enable.
1=DC offset correction disable. 0’b
0=DC offset correction enable.
R/W Channel A receive differential input DC offset correction
disable/enable.
0’b
1=invert phase, 0=default phase 0’b
1=invert phase, 0=default phase 0’b
1=invert phase, 0=default phase 0’b
1=invert phase, 0=default phase 0’b
R/W Invert RCD clock phase (RCD shift by 180 degrees)
R/W Invert RCC clock phase (RCC shift by 180 degrees)
R/W Invert RCB clock phase (RCB shift by 180 degrees)
R/W Invert RCA clock phase (RCA shift by 180 degrees)
BIT
15:0
NAME
Reserved
TABLE 3-18. SPARE STATUS REGISTER
MII REGISTER 19 & 49163, ADDRESSES = 13’h & C00B’h
SETTING
DEFAULT
R/W
DESCRIPTION
BIT
15:9
8:0
NAME
Reserved
ERROR
TABLE 3-19. XGMII ERROR CODE REGISTER
MII REGISTER 22 & 49154, ADDRESSES = 16’h & C002’h
SETTING
DEFAULT
R/W
DESCRIPTION
N/A
1FF’h
R/W
Error Code. These bits allow the ERROR character to be programmed.
Overridden by XAUI_EN, see Table 3-28 and/or Table 3-33
BIT
15:12
11
10
9
8
7:4
3
2
1
0
NAME
Reserved
SLP_D
SLP_C
SLP_B
SLP_A
Reserved
PLP_D
PLP_C
PLP_B
PLP_A
TABLE 3-20. LOOP BACK CONTROL REGISTER
MII REGISTER 23 & 49156, ADDRESSES = 17’h & C004’h
SETTING
DEFAULT R/W
DESCRIPTION
1=enable
0=disable
0’h
R/W
Internal Serial Loop Back Enable. These bits enable the loopback function
for serial data for each individual channel. When high, they route the
internal output of the Serializer to the input of the clock recovery block.
1=enable
0=disable
0’h
R/W
Internal Parallel Loop Back Enable. These bits enable the loopback
function for parallel data for each individual channel. When high, it routes
the internal output of the Deserializer to the parallel input of each channel.
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