BBT3420 Datasheet, PDF (32/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
TABLE 6-12. SERIAL DIFFERENTIAL INPUT TIMING REQUIREMENTS (see Figure 6-12)
SYMBOL
PARAMETER
MIN
TYP
MAX
T_DJ
Deterministic Jitter (Notes 1, 2)
0.7
T_JI
Total jitter tolerance
0.88
NOTES:
1. Jitter specifications include all but 10^-12 of the jitter population.
2. Near end driven by BBT3420 Tx.
UNIT
UI
UI
SYMBOL
T_RESET
T_RSTDVS
T_RSTDVH
T_RSTMFV
TABLE 6-13. RESET AND DEVAD FROM MFD, MFC TIMING (see Figure 6-9)
PARAMETER
MIN
TYP
RSTN Active width
10
Setup from MFD, MFC to RSTN
2
Hold from RSTN to MFD, MFC
1
Delay from RSTN to MFD/C Valid
2
MAX
UNIT
µs
µs
T_REFCLK
T_REFCLK
TABLE 6-14. MDIO INTERFACE TIMING (from IEEE802.3ae-2002) (see Figure 6-10)
SYMBOL
PARAMETER
MIN
TYP
MAX
UNIT
T_MDCD
T_MDS
T_RSTDVH
T_RSTMFV
BBT3420 MDIO out delay from MDC
Setup from MDIO in to MDC
Hold from MDC to MDIO in
Clock Period MDC (Note 1)
MDC Clock HI or LO time (Note 1)
0
300
ns
10
ns
10
ns
50
400
ns
20
160
ns
NOTE:
1. The BBT3420 will accept a much higher MDC clock rate and shorter HI and LO times than the IEEE802.3ae specification (section 22.2.2.11)
requires. Such a faster clock may not be acceptable to other devices on the interface.
SYMBOL
T_RESET
T_RSTBIST
T_BRST
T_BRVD
TABLE 6-15. RESET AND BISTEN TIMING (see Figure 6-11)
PARAMETER
MIN
TYP
RSTN Active width
10
Delay from RSTN to BISTEN
2
BISTEN Inactive width
20
Delay from BISTEN to valid ERR (MFA-D) Value
MAX
UNIT
µs
T_REFCLK
T_REFCLK
T_REFCLK
32