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BBT3420 Datasheet, PDF (20/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver | |||
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BBT3420
TABLE 3-31. LOS STATUS REGISTER (CLAUSE 45)
MII REGISTER 49161, ADDRESS = C009âh
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
15:8
Reserved
7:4
Internal
Fâh
RO
Internal Function (ignore)
3
LOS_D
1 = Signal less than 0âb
RO/LH
Loss Of Signal for RX Inputs of each of 4 channels; signal less
2
LOS_C
threshold
0 = Signal greater
0âb
(Note 1)
than LOS_CONTROL value (see Table 3-28 and/or Table 3-33)
(Note 2)
1
LOS_B
than threshold
0âb
0
LOS_A
0âb
NOTES:
1. These bits are latched high on any LOS condition detected. They are reset low on being read.
2. Please refer to sectionâ3.7.2 Loss of Signal (LOS)â on page 6 for a more detailed description.
TABLE 3-32. MISCELLANEOUS CONTROL REGISTER 1 (CLAUSE 45)
MII REGISTER 49152, ADDRESS = C000âh
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
15:14 Reserved
00âb
Always write to 00âb
13
VDDQ_ASNS_EN 0=enable
1=disable
0âb
R/W Automatically detect VDDQ power supply level and
adjust parallel output buffer driving strength.
12
HSTL_DRIVE
0=enable
1=disable
0âb
R/W Increase parallel output buffer driving strength (if
autosense disabled).
11
SC_RBC
1=source sync
0=source center
0âb
R/W Timing of outgoing Receive Byte Clock (RBC) to
Receive data
10
CODECENA
1=enable if CODE pin hi
0=disable
1âb
R/W Internal 8b/10b Codec enable/disable
9:8 CDET[1:0]
Bit 7 controls positive comma
11âb
detection, Bit 6 controls negative
comma detection
0âb=disable
1âb=enable
R/W Comma Detect Select. These bits enable detection
of positive, negative, or both positive and negative
disparities of comma, or disable detection of either.
7
DSKW_SM_EN 0=disable
1=enable
0âb
R/W Enable De-skew state machine control (Note 1) .
Overridden enabled by XAUI_EN; see Table 3-28
and/or Table 3-33. May not operate correctly unless
the PCS_SYNC_EN bit is also set.
6:5 RCLKMODE
See Table 3-22 for a description of
these bits, and their interaction with
the PSYNC and RETIMER pins.
Received Clock Mode. These two bits, together with
the PSYNC and RETIMER pins, select which clock
the received data is aligned to.
4
PCS_SYNC_EN 0=disable
1=enable
0âb
R/W Enable 8b/10b PCS coding synchronized state
machine (Note 1) to control the byte alignment (IEEE
ëcode-group alignmentâ) of the high speed
deserializer. Overridden enabled by XAUI_EN; see
Table 3-28 and/or Table 3-33.
3
IDLE_D_EN
1=enabled
0=disabled
1âb
R/W Enables IDLE vs. NON-IDLE detection for channel
alignment.
2
ELST_EN
1=enabled
0=disabled
1âb
R/W Enable the elastic function of the receiver buffer
1
A_ALIGN _DIS 1=disabled
0=enabled
1âb
R/W Receiver aligns data on incoming "\/A/" characters
(K28.3). If disabled (default), receiver aligns data on
IDLE to non-IDLE transitions (if bit 3 set). Overridden
enabled by XAUI_EN; see Table 3-28 and/or Table 3-
33.
20
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