BBT3420 Datasheet, PDF (6/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
TABLE 3-2. PRE-EMPHASIS CONTROL
CLAUSE 22
CLAUSE 22
ADDRESS 1C’h OR ADDRESS 1C’h OR
CLAUSE 45
CLAUSE 45
ADDRESS C005’h ADDRESS C005’h
BIT 15
BIT 14
0
0
PRE-EMPHASIS
VALUE =
(V_PPOUT/V_PP)-1
No Pre-Emphasis
0
1
0.18
1
0
0.38
1
1
0.75
1
1
0
0
Vpp
Vppout
Bit
Time
Bit
Time
Bit
Time
FIGURE 3-1. PRE-EMPHASIS OUTPUT ILLUSTRATION
3.6 Output Select – Serial Loopback
In normal mode, the serialized transmission TD[A..D][9..0]
data will be placed on TX[A..D]P/N. When serial loopback is
activated, Tx[AÖD] is internally looped back to Rx[AÖD]
respectively.
3.7 Receiver
The receiver detects and recovers the serial clock and data
from the received data stream. After acquiring bit
synchronization, the BBT3420 normally searches the serial
bit stream for the occurrence of a comma character to obtain
byte synchronization (byte alignment). The receiver then
performs channel alignment and clock compensation, as
desired. These are each discussed in the sections below.
3.7.1 Input Equalization and Transmission Line
Termination
An equalizer has been added to each receiver input buffer,
which boosts high-frequency edge response. The boost
factor can be selected from 0 to F’h through MDIO. The
MDIO register at address 1C’h (Clause 22), and/or C005’h
(Clause 45), see Table 3-27, controls the boost value of the
equalizer functions. A nominal 100Ω on-chip transmission-
line termination resistor is integrated with the input equalizer,
eliminating the requirement of an external termination
resistor. This greatly improves the effectiveness of the
termination, providing the best possible signal integrity.
3.7.2 Loss of Signal (LOS)
Loss of signal is an indication of gross signal error
conditions. It is not an indication of signal coding health. It
may be caused by poor connections, insufficient voltage
swings, or out-of-range signal frequency. If any of these
conditions occurs, the SIG_DET pin will be de-asserted. In
addition, the MDIO MF_CTRL register bits (Address 10’h for
Clause 22 format, Table 3-15, and/or C001’h for Clause 45
format, Table 3-33) can be set to have the MF[A-D] pins
provide per-channel indication of Loss of Signal conditions,
the threshold being set by the MDIO LOS_CONTROL
register bits at Address 1D’h for Clause 22 format and/or
C001’h for Clause 45 format, Table 3-28 and/or Table 3-33
respectively. The LOS indication is also available directly in
the MDIO status registers, Address 01’h in Clause 22 format,
see Table 3-9, and/or Address C009’h in Clause 45 format,
see Table 3-31. The combination of all four drives the
SIG_DET pin (see Table 4-6), and contributes to the
RX_FAULT bit in the IEEE Status Register 2 at address
(00)08’h (Table 3-14) and the LOCAL_FLT bit in Register
0001’h, 1 in Table 3-10 (Clause 45 only).
As mentioned previously, LOS is designed as an indicator.
The listed LOS threshold is for reference only, it is not
designed to measure signal amplitude. Under nominal
operation conditions, the actual LOS threshold is at a signal
swing (single-ended peak-peak) lower or around the
datasheet specified threshold. For a low LOS threshold
setting, LOS may never be asserted due to noise.
3.7.3 Clock and Data Recovery
The line rate receive clock is extracted from the transition-
rich 10-bit coded serial data stream independently on each
channel. The data rate of the received serial bit stream for
XAUI should be 3.125Gbps ±100ppm to guarantee proper
reception (and similarily for other data rates). The receive
clock locks to the input within 2µs after a valid input data
stream is applied. The received data is de-serialized and
byte-aligned.
The CDR unit will inherently acquire synchronization,
provided the signal level is adequate, and the frequency is
within the specified range of the local reference clock. If
synchronization is lost due to an invalid signal (e.g.
disconnect, out of range voltage swing, out of range
frequency, etc.), then the high-speed receive clock will free
run frequency-locked to the transmit clock.
3.7.4 Byte Alignment (code-group alignment)
Unless the CDET bits of the MDIO Register at address 10’h
(Table 3-15, Clause 22) and/or C000’h (Table 3-32, Clause
45) are turned off, the Byte Alignment Unit is activated. The
Byte Alignment Unit searches the coded incoming serial
stream for a sequence defined in IEEE 802.3-2002
subclause 36.2.4.8 as a “comma”. A comma is the sequence
“0011111” or “1100000” and is uniquely located in a valid
8b/10b coded data stream, appearing as the start of some
6