BBT3420 Datasheet, PDF (21/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
TABLE 3-32. MISCELLANEOUS CONTROL REGISTER 1 (CLAUSE 45) (Continued)
MII REGISTER 49152, ADDRESS = C000’h
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
0
CAL_EN
1=enabled
0=disabled
1’b
R/W Enable de-skew calculator of receiver buffer
NOTE:
1. These state machines are implemented according to 802.3ae-2002 clause 48.
TABLE 3-33. MISCELLANEOUS CONTROL REGISTER 2 (CLAUSE 45)
MII REGISTER 49153 ADDRESS = C001’h
BIT
15
NAME
SETTING
DEFAULT R/W
SHRT_BIST 1 = Short BIST Loop pattern 0’b
R/W
0 = Long BIST Loop pattern
DESCRIPTION
Short is 13458 Byte pattern, Long is 2²³-1 Byte Pattern (plus 9
/K/ "Comma" bytes)
14:13 Reserved
12
BIST_EN
1 = enable BIST Pattern
0’b
0 = disable
R/W
Built In Self Test (BIST); may also be enabled by the BIST_EN
pin or via the JTAG system.
11
XAUI_EN 1 = enable
0 = disable
0’b
R/W
Enables all XAUI features per 802.3ae-2002. It is equivalent to
setting the following configuration bits (but does not change the
actual value of the corresponding MDIO registers’ bits):
TRANS_EN (reg C001’h)
AKR_EN (reg1D’h/C001’h)
A_ALIGN_DIS: 0’b (reg19’h/C001’h)
PCS_SYNC_EN (reg1D’h/C001’h)
DSKW_SM_EN (reg1D’h/C001’h)
ERROR Code = 1FE’h (reg 16’h)
10:8
LOS_Control 0’h = 160mVp-p
1’h = 240mVp-p
2’h = 200mVp-p
3’h = 120mVp-p
4’h = 80mVp-p
else = 160mVp-p
000’b
R/W
Set the threshold voltage for the Loss Of Signal (LOS)
detection circuit. Nominal levels are listed for each control
value. (Note 2)
7
SC_TBC
1=source sync
0=source center
0’b
R/W
Timing of incoming Transmit Byte Clock (TBC) to transmit data
6
AKR_EN
1 = enable pseudo-random 0’b
R/W
Enable pseudo-random A/K/R (Note 1) in Inter Packet Gap
A/K/R
(IPG) on transmitter side (vs. /K/ only)
0 = /K/ only
5
TRANS_EN 1=enable
0’b
R/W
This bit enables the transceiver to translate an IDLE pattern in
0=disable
the XGMII data (matching the value of register 1B’h) to and
Overridden by XAUI_EN,
from the XAUI IDLE /K/ comma character or /A/, /K/ & /R/.
see bit 11
4
IPON
1=enable
0=disable
1’b
R/W
Internal Parallel Output Enable
3
TX_SDR
1 = SDR
0 = DDR
0’b
R/W
Single data rate on XGMII interface of transmitter.
2:0
MF_CTRL 0 = BIST_ERR
1 = LOS
2 = Reserved
3 = RC[A:D]
4 = TXFIFO_ERR
5 = AFIFO_ERR
6 = EFIFO_ERR
00’b
R/W
Control the functions of multi-function pins MF[A-D].
RC[A:D]: recovered clock for each channel [A:D].
NOTES:
1. These state machines are implemented according to 802.3ae-2002 clause 48.
2. Please refer to section “3.7.2 Loss of Signal (LOS)” on page 6 for a more detailed description.
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