BBT3420 Datasheet, PDF (23/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
4 Pin Specifications for BBT3420
The BBT3420 device is packaged in a 289-pin HSPBGA. The terminals are grouped in tables by functionality.
PIN#
J3, J2
A10
F16, M16, U10
A11
F17, M17, U11
NAME
RFCP/RFCN
TCA
TCB, TCC,
TCD
RCA
RCB, RCC,
RCD
TABLE 4-1. CLOCK PINS
TYPE
DESCRIPTION
Input
Differential Reference Input Clock
Input
Transmit Data Clock, Channels A. The data on TDA(0 - 9) islatched on the rising
and falling edges of TCA. When PSYNC is high, TCA acts as the transmit clock for
all channels.
Input
Transmit Data Clock, Channels B - D. When PSYNC is low, the data on TDx(0 - 9)
is latched on the rising and falling edges of the transmit clocks. When PSYNC is
high, these pins are ignored.
Output
Receive Data Clock, Channels A. The data on RDA(0 - 9) is output on the rising and
falling edges of RCA. When PSYNC is high, RCA acts as the receive clock for all
channels.
Output
Receive Data Clock, Channels B - D. When PSYNC is low, the data on RDx(0 - 9)
is output on the rising and falling edges of the receive clocks. When PSYNC is high,
these pins are undefined.
PIN#
NAME
D5, D6, F4, G4, M4, L4, P5,
P6
TXAP/TXAN
TXBP/TXBN
TXCP/TXCN
TXDP/TXDN
B5, B6, F2, G2, M2, L2,T5, T6 RXAP/RXAN
RXBP/RXBN
RXCP/RXCN
RXDP/RXDN
TABLE 4-2. SERIAL SIDE DATA PINS
TYPE
DESCRIPTION
Output Transmit Differential Pairs, Channel A - D. CML high-speed serial outputs.
Input
Receive Differential Pairs, Channel A - D. CML high-speed serial inputs.
PIN#
C8, B8, A8, E9, D9, C9,
E10, D10
C10
NAME
TDA(0-7)
TDA8
B10
TDA9
C11, B11, E12, D12,
C12, C13, B13, A13
B14
RDA(0-7)(0-7)
RDA8
A14
RDA9
TABLE 4-3. PARALLEL SIDE DATA PINS
TYPE
DESCRIPTION
Input
Transmit Data Pins, Channel A. Parallel data on this bus is clocked on the rising and
falling edges of TCA.
Input
Transmit Data/ K-code Flag, Channel A. When CODE is low, this pin is the 9th bit of an
8b10b-encoded/10b-encoded byte to be transmitted. When CODE is high, this pin acts
as the K-character generator indicator. When high, this pin causes the data on TDA(0-
7) to be encoded into a K-character. Data on this pin is clocked on the rising and falling
edges of TCA.
Input
Transmit Data Pin, Channel A. When CODE is low, this pin is the 10th bit of an 8b/10b-
encoded byte. When CODE is high, this pin is undefined. Data on this pin is clocked on
the rising and falling edges of TCA.
Output
Receive Data Pins, Channel A. Parallel data on this bus is valid on the rising and falling
edges of RCA.
Output
Receive Data/ K-code Flag, Channel A. When CODE is low, this pin is the 9th bit of a
received 8b/10b-encoded byte. When CODE is high, this pin acts as the K-character
flag. When high, this indicates the data on RDA(0-7) is a valid K-character. Data on this
pin is valid on the rising and falling edges of RCA.
Output
Receive Data Pin/ Error Detect, Channel A. When CODE is low, this pin is the 10th bit
of an 8b/10b-encoded byte. When CODE is high, this pin goes high to signify the
occurrence of either a parity error or an invalid code word during the decoding of the
received data. Data on this pin is valid on the rising and falling edges of RCA.
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