BBT3420 Datasheet, PDF (17/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
BIT
15:2
1:0
TABLE 3-21. RECEIVE CLOCK MODE REGISTER (CLAUSE 22)
MII REGISTER 24, ADDRESS = 18’h (CLAUSE 22)
NAME
SETTING
DEFAULT R/W
DESCRIPTION
Reserved
RCLKMODE Depends on RETIMER and 01’b
PSYNC pins (Table 4-6).
See settings in Table 3-22.
R/W Received Clock Mode. These two bits, together with the PSYNC
and RETIMER pins, select which clock the received data is aligned
to.
TABLE 3-22. RCLKMODE BIT SETTINGS = 18’h.1:0 (CLAUSE 22) or C000’h.6:5 (CLAUSE 45)
PIN NAME, LOGIC LEVEL
RETIMER PSYNC
REGISTER CHANNEL
BIT SETTING ALIGNMENT
RCLKMODE BITS, and PIN VALUES, to
RECEIVE DATA CLOCK ALIGNMENT
0
0
XX
No
Local Reference Clock
0
1
XX
Yes
Local Reference Clock
X
0
11’b
No
Local Reference Clock
X
1
11’b
Yes
Local Reference Clock
1
0
10’b
No
Recovered Clock for each individual channel
1
1
10’b
Yes
Recovered Clock for Channel A
1
X
0X’b
Yes
Recovered Clock for Channel A
TABLE 3-23. PCS ALIGNMENT AND SYNC STATUS REGISTER (CLAUSE 45)
MII REGISTER 24, ADDRESS = 18’h (CLAUSE 45)
BIT
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
15:13
Reserved
12
Chan_ALIGN 1 = aligned
0’b (Note 1) RO
Four channels are aligned
11
Test_P_Able 0
0’b
RO
No IEEE802.3 test patterns (but see BIST discussion)
10:4
Reserved
3
SYNC_D
1 = channel
0’b (Note 1) RO
Reflects the PCS_SYNC byte alignment state machine
synchronized
condition; not valid if not enabled (see Table 3-28 and/or
2
SYNC_C
0 = channel not
0’b (Note 1) RO
Table 3-32)
1
SYNC_B
synchronized
0’b (Note 1) RO
0
SYNC_A
0’b (Note 1) RO
NOTE:
1. These bits contribute to the Receive Local Fault bit RX_FAULT in the IEEE XGXS Status2 Register (see Table 3-14). Also, these bits will reflect
the input signal status if DSKW_SM_EN is enabled.
BIT
15:4
3
2
1
0
TABLE 3-24. SYMBOL AND ELASTICITY CONTROL (CLAUSE 22)
MII REGISTER 25, ADDRESS = 19’h
NAME
SETTING
DEFAULT R/W
DESCRIPTION
Reserved
IDLE_D_EN 1=enabled, 0=disabled 1’b
R/W
Enables IDLE vs. nonIDLE detection for Channel Alignment and
Elasticity operations.
ELST_EN
1=enabled, 0=disabled 1’b
R/W
Enable the elastic function of the receiver buffer
A_ALIGN _DIS 1=enabled, 0=disabled 1’b
R/W
Receiver aligns data on incoming "/A/" characters (K28.3). If disabled
(default), receiver aligns data on IDLE to nonIDLE transitions (if bit 3
set). Overridden by XAUI_EN, see Table 3-28
CAL_EN
1=enabled, 0=disabled 1’b
R/W
Enable de-skew calculator of receiver buffer. (see Channel Alignment
discussion)
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