BBT3420 Datasheet, PDF (25/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
PIN#
R10
T10
R11, T11, N12, P12,
R12, R13, T13, U13
T14
U14
PIN#
B3
A2
B2
A3
A1
NAME
TDD8
TDD9
RDD(0-7)
RDD8
RDD9
TABLE 4-3. PARALLEL SIDE DATA PINS (Continued)
TYPE
DESCRIPTION
Input
Transmit Data/ K-code Flag, Channel D. When PSYNC is low, data on this pin is clocked
on the rising and falling edges of TCD. When PSYNC is high, data on this bus is clocked
on the rising and falling edges of TCA. When CODE is low, this pin is the 9th bit of an
8b/10b-encoded byte to be transmitted. When CODE is high, this pin acts as the K-
character generator indicator. When high, this pin causes the data on TDD(0-7) to be
encoded into a K-character.
Input
Transmit Data Pin, Channel D. When PSYNC is low, data on this pin is clocked on the
rising and falling edges of TCD. When PSYNC is high, data on this bus is clocked on the
rising and falling edges of TCA. When CODE is low, this pin is the 10th bit of an 8b/10b-
encoded byte. When CODE is high, this pin is undefined.
Output
Receive Data Pins, Channel D. When PSYNC is low, parallel data on this bus is valid on
the rising and falling edges of RCD. When PSYNC is high, data on this bus is valid on
the rising and falling edges of RCA.
Output
Receive Data/ K-code Flag, Channel D. When PSYNC is low, data on this pin is valid on
the rising and falling edges of RCD. When PSYNC is high, data on this pin is valid on
the rising and falling edges of RCA. When CODE is low, this pin is the 9th bit of a
received 8b/10b-encoded byte. When CODE is high, this pin acts as the K-character
flag. When high, this indicates the data on RDD(0-7) is a valid K-character.
Output
Receive Data Pin/ Error Detect, Channel D. When PSYNC is low, data on this pin is valid
on the rising and falling edges of RCD. When CODE is low, this pin is the 10th bit of an
8b/10b-encoded byte. When CODE is high, this pin goes high when to signify the
occurrence of either a parity error or an invalid code word during the decoding of the
received data.
NAME
TDI
TDO
TMS
TCLK
TRSTN
TABLE 4-4. JTAG INTERFACE
TYPE
Input
JTAG Input Data
(w/pullup)
Output JTAG Output Data
Input
JTAG Mode Select
(w/pullup)
Input
JTAG Clock
(w/pulldown)
Input
JTAG Reset
(w/pullup)
DESCRIPTION
PIN#
U3
U2
R1, T1, T3, T2, R2
NAME
MDIO
MDC
PADR(0-4)
TABLE 4-5. MANAGEMENT DATA INTERFACE
TYPE
DESCRIPTION
I/O
Management Address/Data I/O
Input
Management Interface Clock
Input
Management Address (PHYAD for Clause 22, PRTAD for Clause 45). See also
MFD & MFC in next table for DEVAD control in Clause 45.
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