BBT3420 Datasheet, PDF (18/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
BIT
15
14
13:8
7
6
5
4
3:0
TABLE 3-25. ERROR FLAGS
MII REGISTER 26 & 49158, ADDRESSES = 1A’h & C006’h
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
CNTM_ERR 1 = error, 0 = no error 0’b
RO
Error flag of receiver buffer (deskew misalignment)
CNTS_ERR 1 = error, 0 = no error 0’b
RO
Error flag of receiver buffer (offset sum error)
Reserved
BIST_ERR_D 1 = error
0 = no error
BIST_ERR_C
0’b
RO
Error flags for BIST system.
0’b
RO
BIST_ERR_B
0’b
RO
BIST_ERR_A
0’b
RO
Reserved
BIT
15:8
7:0
NAME
Reserved
XG_IDLE
TABLE 3-26. XGMII-SIDE IDLE CODE
MII REGISTER 27 & 49155, ADDRESSES = 1B’h & C003’h
SETTING
DEFAULT
R/W
DESCRIPTION
07’h
R/W
IDLE pattern on XGMII data buses for translation to/from
XAUI IDLEs
BIT
15:14
13:4
3:0
TABLE 3-27. EQUALIZATION AND PRE-EMPHASIS CONTROL
MII REGISTER 28 & 49157, ADDRESSES = 1C’h & C005’h
NAME
SETTING
DEFAULT
R/W
DESCRIPTION
PRE_EMP
0’h = no pre-emp
1’h = 0.18 pre-emp
2’h = 0.38 pre-emp
3’h = 0.75 pre-emp
0’h
R/W
Configure the level of pre-emphasis (nominal levels
indicated)
Reserved
EQ_COEFF 0’h = no hf boost in equalizer. 0’h
F’h = boost is maximum
R/W
Configuration of the equalizer
BIT
15
14
13
12:11
10
NAME
Reserved
XAUI_EN
DSKW_SM_EN
Reserved
PCS_SYNC_EN
TABLE 3-28. MISCELLANEOUS CONTROL REGISTER 3 (CLAUSE 22)
MII REgister 29, ADDRESS = 1D’h
SETTING
DEFAULT R/W
DESCRIPTION
1 = enable
0 = disable
0=disable
1=enable
0=disable
1=enable
0’b
R/W
Enables all XAUI features per 802.3ae-2002. It is equivalent to
setting the following configuration bits (but does not change
the actual value of the corresponding MDIO registers’ bits):
TRANS_EN (reg 10’h bit3)
AKR_EN (reg1D’h bit2)
A_ALIGN _DIS: 0’b (reg19’h bit1)
PCS_SYNC_EN (reg1D’h bit10)
DSKW_SM_EN (reg1D’h bit13)
ERROR Code = 1FE’h (reg 16’h)
0’b
R/W
Enable De-skew state machine control (Note 1). Forced
enabled by XAUI_EN. May not operate correctly unless the
PCS_SYNC_EN bit is also set.
00’b
Always write to 00’b
0’b
R/W
Enable 8b/10b PCS coding synchronized state machine
(Note 1) to control the byte alignment (IEEE ëcode-group
alignment’) of the high speed deserializer
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