BBT3420 Datasheet, PDF (19/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

BBT3420
TABLE 3-28. MISCELLANEOUS CONTROL REGISTER 3 (CLAUSE 22) (Continued)
MII REgister 29, ADDRESS = 1D’h
BIT
NAME
SETTING
DEFAULT R/W
DESCRIPTION
9
TX_SDR
1 = SDR
0 = DDR
0’b
R/W
Single data rate on XGMII interface of transmitter.
8
V_DDQ_ASNS_EN 0=enable
1=disable
0’b
R/W
Automatically detect V_DDQ power supply level and adjust
parallel output buffer driving strength.
7
HSTL_DRIVE
0=enable
1=disable
0’b
R/W
Increase parallel output buffer driving strength (if autosense
disabled).
6:4
LOS_CONTROL 0’h = 160mV_P-P
000’b
1’h = 240mV_P-P
2’h = 200mV_P-P
3’h = 120mV_P-P
4’h = 80mV_P-P
else = 160mV_P-P
3
SC_RBC
1=source sync
0’b
0=source center
R/W
Set the threshold voltage for the Loss Of Signal (LOS)
detection circuit. Nominal levels are listed for each control
value. Note 2
R/W
Timing of outgoing Receive Byte Clock (RBC) to Receive data
2
AKR_EN
1 = enable random 0’b
A/K/R
0 = /K/ only
R/W
Enable pseudo-random A/K/R (Note 1) in Inter Packet Gap
(IPG) on transmitter side (vs. /K/ only)
1
SOFT_RESET Write 1 to initiate. 0’b
R/W SC Reset the entire chip except MII register settings
0
Reserved
NOTES:
1. These state machines are implemented according to 802.3ae-2002 clause 48.
2. Please refer to section “3.7.2 Loss of Signal (LOS)” on page 6 for a more detailed description.
BIT
15:0
NAME
reserved
TABLE 3-29. SPECIAL TEST FUNCTION CONTROL REGISTER
MII REGISTER 30 & 49159, ADDRESSES = 1E’h & C007’h
SETTING
DEFAULT
R/W
DESCRIPTION
AAAA’h
R/W
Internal Function. DO NOT ALTER THIS REGISTER in BBT3420
BIT
15:4
3
2
1
0
NAME
reserved
HALF_RATED
HALF_RATEC
HALF_RATEB
HALF_RATEA
TABLE 3-30. HALF RATE CLOCK CONTROL REGISTER
MII REGISTER 31 & 49160, ADDRESSES = 1F’h & C008’h
SETTING
DEFAULT
R/W
DESCRIPTION
0’h
R/W
1’b = half rate clock 0’b
R/W
Channel D is running at half-rate clock speed
1’b = half rate clock 0’b
R/W
Channel C is running at half-rate clock speed
1’b = half rate clock 0’b
R/W
Channel B is running at half-rate clock speed
1’b = half rate clock 0’b
R/W
Channel A is running at half-rate clock speed
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