BBT3420 Datasheet, PDF (3/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver

HS_TX_CLK
TX+
TX-
Pre-empahsis
BBT3420
8B/10B
Encoder
&
AKR
Generator
TX FIFO
&
Error and
Orderset
Detector
BIST
Pattern
Generator
CODE
BISTEN
PLP
DDR
Input
Registers
TD[9:0]
TBC
RX+
RX-
SIGDET
SLP
REF_CLK
100 Ohm
Termination,
Equalizer,
Signal
Detect
Clock and
Data
Recovery
10B/8B
Decoder
RX FIFO
Deskew
Logic
BIST
Pattern
Analyzer
FIGURE 1-3. FUNCTIONAL BLOCK DIAGRAM OF A SINGLE CHANNEL
DDR
Output
Registers
RD[9:0]
RBC
2 General Description
The BBT3420 is a quad 8-bit/10-bit parallel-to-serial and
serial-to-parallel transceiver device ideal for high-bandwidth
interconnection between line cards, serial backplanes, or
optical modules, over interconnect media such as Printed
Circuit Board (PCB) FR-4 traces or copper cables.
Each independent transceiver channel in BBT3420 is
capable of operating at 2.488-3.1875Gbps at full-rate, and
1.244-1.59375Gbps at half-rate. The four on-chip
transceivers shown in Figure 1-2 can also be configured as
a single 10 Gigabit Attachment Unit Interface (XAUI), for
both 10G Ethernet and 10G Fiber Channel or proprietary
backplane interfaces, providing up to 12.75Gbps of data
throughput at full duplex. The BBT3420 also supports the 10
Gigabit Media Independent Interface (XGMII) on the parallel
interfaces. The device can be used as an XGMII Extended
Sublayer (XGXS) device to support longer PCB traces
between optical transceiver modules and switch fabrics, as
shown in Figure 1-1.
As shown in Figure 1-3, each transceiver channel in
BBT3420 contains a serializer, a deserializer, an 8b/10b
encoder and decoder, as well as elastic buffers that provide
the interface for serial data transmission and data recovery.
Both the receive equalization and the transmit pre-emphasis
are provided on each of the channels to maximize
performance. In addition, a programmable receive FIFO in
each channel aligns all incoming serial data to the local clock
domain, adding or removing IDLE sequences as needed.
This in return will eliminate the need for multiple clock
domains for the interfaced ASIC device to the transceiver.
Each transceiver channel can also be configured to operate
as a non-encoded 10-bit transceiver, allowing long strings of
consecutive 1's or 0's (up to 512 bits). This feature enables
the BBT3420 to accommodate proprietary encoded data
links.
On each channel, the transmitter accepts up to 10-bit wide
parallel SSTL_2 or HSTL Class I/O (Figure 2-1) data, which
is then serialized into high-speed NRZ (Non-Return to Zero)
serial streams. The effective serial output impedance is
nominally 150Ω differential.
The BBT3420 transceiver can be configured via pins and
through the Management Data Input/Output (MDIO)
interface specified in IEEE 802.3 Clause 22 or Clause 45.
The device supports both the 5-bit PHY address for Clause
22 and the 5-bit port address for Clause 45. The four device
addresses for Clause 45 are user selectable. The device
also supports the Built-in Self Test (BIST) and IEEE 1149.1
(JTAG) for self-test purposes including serial and parallel
loopback under either external pin or MDIO control, and
Pseudo Random Bit Sequence (PRBS) generation and
verification.
The BBT3420 is assembled in a 289-pin 19mm x 19mm
HSBGA package. The device can operate with a single 1.8V
supply and dissipates only 250mW per channel.
VTT=VDDQ/2
50Ω
Zo=50Ω
VREF= VDDQ/2
FIGURE 2-1. SSTL_2/HSTL CLASS I I/O
3