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BBT3420 Datasheet, PDF (11/38 Pages) Intersil Corporation – Quad 2.488-3.1875Gbps/Channel Transceiver | |||
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BBT3420
RETIMER function. The device may be set to respond to any
registers for PHY XS and DTE XS devices (they may be
one of four DEVAD values, (4, 5, 30 or 31) by controlling the
level on the MFC and MFD pins at the end of reset. These
accessed identically through any of the implemented DEVAD
address values), and 11 of the 32k (215) allowed Vendor
pins are normally outputs, but become inputs when RSTN is
active, and so may be pulled to the desired value by
moderate value resistors (~5kâ¦), which will not affect the
normal operation of the pins when outputs. The value on
these pins will be latched at the rising edge of RSTN. The
coding is shown in Table 3-5. A weak pullup is built into
these pins, so that if unwired, they will default to DEVAD = 5.
See Table 6-13 and Figure 6-9 for the timing of these
signals. The Clause 45-accessible registers are listed in
Table 3-7. These register addresses are independent of the
DEVAD value, including the âVendor Definedâ DEVAD values
30 & 31; thus registers 30.8 & 31.8 include the RX_FAULT
and TX_FAULT bits.
Each individual device may have up to 216 (65,536)
registers. The BBT3420 implements 11 of the IEEE-defined
Specific registers. The latter have been placed in the block
beginning at C000âh so as to avoid the areas currently
defined as for use by the XENPAK module and similar MSA
devices, to facilitate use of the BBT3420 in systems using
such modules and/or devices.
In order to align the registers and bits as closely as possible
to the new IEEE Clause 45 standard, while maintaining
compatibility with previous versions of the part before the
Clause 45 interface was defined, which used only the
Clause 22 interface, the control and status bits are differently
distributed among the registers in the two formats. The
Clause 22 registers are listed in Table 3-6, and the Clause
45 registers in Table 3-7.
TABLE 3-6. MDIO REGISTERS IN CLAUSE 22 FORMAT
MII REGISTERS
ADDRESS
NAME
DESCRIPTION
DEFAULT
R/W
DETAILS
00âh Control
Reset, Enable serial loop back mode.
2040âh
R/W
Table 3-8
01âh Status
Device Present & LOS
800Fâh (Note 2) RO
Table 3-9
02:3âh ID Code
Manufacturer and Device OUI & IDs
01839C5Vâh RO
See (Note 1)
04âh Speed Ability
10Gbps Ability
0001âh
RO
Table 3-11
05âh IEEE Devices
Devices in Package, Clause 22 capable
0021âh (Note 3) RO
Table 3-12
06âh Vendor Devices
Vendor Specific Devices in Package
0000âh (Note 3) RO
Table 3-13
08âh Fault Status
Transmit & Receive Fault
8000âh (Note 2) RO/LH
Table 3-14
10âh Misc. Control 1
Channel, Comma, TX Idle, MF controls
00C0âh
R/W
Table 3-15
11âh Misc. Control 2
Code, Comma, Codec, TCx controls
0140âh
R/W
Table 3-16
12âh Special Control Register DC Offset & RC[A:D] phase shift control
0000âh
R/W
Table 3-17
13âh Resvd2
Spare Status
0000âh
RO
Table 3-18
16âh ERROR
Sets XGMII ERROR Code
0FFâh
R/W
Table 3-19
17âh Loop Back
Controls Serial & Parallel Loopback
0000âh
R/W
Table 3-20
18âh Receive Clock
Receive Clock Mode
0001âh
R/W
Table 3-21
19âh Symbol
IDLE, Alignment and Elasticity Control
000Fâh
R/W
Table 3-24
1Aâh Errors
Error Flags
0000âh (Note 2) RO
Table 3-25
1Bâh XGMII IDLE
XGMII-side IDLE Code
0007âh
R/W
Table 3-26
1Câh Boost/Pre-emp
Boost and Pre-emphasis Control
0000âh
R/W
Table 3-27
1Dâh
1Eâh
Misc. Control 3
Internal Test
VDDQ, LOS, RC timing, /A/K/R/
0000âh
AAAAâh
R/W
Table 3-28
R/W
Table 3-29
1Fâh Half Rate
Half-rate clock mode enable
0000âh
R/W
Table 3-30
NOTES:
1. âVâ is a version number. See under â3.15 JTAGâ on page 22 for a note about the version number.
2. Read value depends on status signal values. Value shown indicates ânormalâ operation.
3. Read value depends on DEVAD setting, see Table 3-5 and Figure 6-9 for details.
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